Python.cpp

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#include <vector>
#include <list>

#include "IOobject.h"
#include "IOdata.h"
#include "Interface.h"
#include "RAM.h"
#include "Register.h"
#include "UsbI2cBus.h"
#include "UsbSpiBus.h"

#include <boost/python.hpp>
#include <boost/python/suite/indexing/vector_indexing_suite.hpp>

using namespace boost::python;

struct InterfaceWrap : Interface, wrapper<Interface>
{
  void help(){this->get_override("help")();};
  StatusCode init(){return this->get_override("init")();};
  void reset(){this->get_override("reset")();};
  void update(){this->get_override("update")();};
  StatusCode read(IOdata*){return this->get_override("read")();};
  StatusCode write(IOdata*){return this->get_override("write")();};
};

BOOST_PYTHON_MODULE(libCatCore)
{
  class_< std::vector<unsigned long> >("ULongVec")
    .def(vector_indexing_suite< std::vector<unsigned long> >())
    ;

  class_<InterfaceWrap, boost::noncopyable, bases<Element> >("Interface")
    .def("help",pure_virtual(&Interface::help))
    .def("init",pure_virtual(&Interface::init))
    .def("reset",pure_virtual(&Interface::reset))
    .def("update",pure_virtual(&Interface::update))
    .def("read",pure_virtual(&Interface::read))
    .def("write",pure_virtual(&Interface::write))
  ;

  class_<UsbI2cBus, bases<Interface> >("UsbI2cBus")
    .def("help"      ,&UsbI2cBus::help)
    .def("init"      ,&UsbI2cBus::init)
    .def("reset"     ,&UsbI2cBus::reset)
    .def("update"    ,&UsbI2cBus::update)
    .def("regData"   ,&UsbI2cBus::regData,return_value_policy<reference_existing_object>())
    .def("regAddress",&UsbI2cBus::regAddress,return_value_policy<reference_existing_object>())
  ;

  class_<UsbSpiBus, bases<Interface> >("UsbSpiBus")
    .def("help"          ,&UsbSpiBus::help)
    .def("init"          ,&UsbSpiBus::init)
    .def("reset"         ,&UsbSpiBus::reset)
    .def("update"        ,&UsbSpiBus::update)
    .def("setTxNeg"      ,&UsbSpiBus::setTxNeg)
    .def("txNeg"         ,&UsbSpiBus::txNeg)
    .def("setRxNeg"      ,&UsbSpiBus::setRxNeg)
    .def("rxNeg"         ,&UsbSpiBus::rxNeg)
    .def("setASS"        ,&UsbSpiBus::setASS)
    .def("aSS"           ,&UsbSpiBus::aSS)
    .def("setLSBFirst"   ,&UsbSpiBus::setLSBFirst)
    .def("lSBFirst"      ,&UsbSpiBus::lSBFirst)
    .def("setClockDivider",&UsbSpiBus::setClockDivider)
    .def("clockDivider"   ,&UsbSpiBus::clockDivider)
    .def("regCtrl"       ,&UsbSpiBus::regCtrl,return_value_policy<reference_existing_object>())
    .def("regClockDivider",&UsbSpiBus::regClockDivider,return_value_policy<reference_existing_object>())
    .def("regSlaveSelect",&UsbSpiBus::regSlaveSelect,return_value_policy<reference_existing_object>())
    .def("regRxData"     ,&UsbSpiBus::regRxData,return_value_policy<reference_existing_object>())
    .def("regTxData"     ,&UsbSpiBus::regTxData,return_value_policy<reference_existing_object>())
  ;

  unsigned long int (IOdata::*dataU8x) (unsigned long int) = (&IOdata::dataU8);
  unsigned long int (IOdata::*dataU16x)(unsigned long int) = (&IOdata::dataU16);
  unsigned long int (IOdata::*dataU32x)(unsigned long int) = (&IOdata::dataU32);

  class_<IOdata, bases<Object> >("IOdata")
    .def("setAddress"            ,&IOdata::setAddress)
    .def("setHeader"            ,&IOdata::setHeader)
    .def("setSubAddress"         ,&IOdata::setSubAddress)
    .def("setOutputSelect"       ,&IOdata::setOutputSelect)
    .def("setMode"               ,&IOdata::setMode)
    .def("setWordSize"           ,&IOdata::setWordSize)
    .def("setLength"             ,&IOdata::setLength)
    .def("setBlock"              ,&IOdata::setBlock)
    .def("setBus"                ,&IOdata::setBus)
    .def("address"               ,&IOdata::address)
    .def("header"                ,&IOdata::header)
    .def("subAddress"            ,&IOdata::subAddress)
    .def("outputSelect"          ,&IOdata::outputSelect)
    .def("mode"                  ,&IOdata::mode)
    .def("wordSize"              ,&IOdata::wordSize)
    .def("length"                ,&IOdata::length)
    .def("block"                 ,&IOdata::block)
    .def("bus"                   ,&IOdata::bus)
    .def("dump"                  ,&IOdata::dump)
    .def("defU8"                 ,&IOdata::defDataU8)
    .def("detU16"                ,&IOdata::defDataU16)
    .def("detU32"                ,&IOdata::defDataU32)
    .def("setU8"                 ,&IOdata::setU8)
    .def("setU16"                ,&IOdata::setU16)
    .def("setU32"                ,&IOdata::setU32)
    .def("dataU8"                ,dataU8x)
    .def("dataU16"               ,dataU16x)
    .def("dataU32"               ,dataU32x)
  ;

  class_<IOobject, bases <Element> >("IOobject")
    .def("help",  &IOobject::help)
    .def("init",  &IOobject::init)
    .def("reset", &IOobject::reset)
    .def("update",&IOobject::update)
    .def("setAddress",&IOobject::setAddress)
    .def("address"   ,&IOobject::address)
    .def("io",    &IOobject::io,return_value_policy<reference_existing_object>())
    .def("read",  &IOobject::read)
    .def("write", &IOobject::write)
    .def("dump"  , &IOobject::dump) 
    ;

  class_<Register, bases <IOobject> >("Register")
    .def("setBit", &Register::setBit)
    .def("getBit", &Register::getBit)
    ;

  class_<RAM, bases <IOobject> >("RAM")
    .def("setSize", &RAM::setSize)
    .def("raz",     &RAM::raz)
    ;
  ;

}