ICECALv3.cpp

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//------------------------------------------------------------------------------
//
//  Package    : ICECALv3
//
//  Description:
//
//  Author(s)  : Joan Mauricio
//  Date       : 2014/05/16
//
//------------------------------------------------------------------------------

// local include file
#include "ICECALv3.h"

//Constructor
ICECALv3::ICECALv3(){
    setType("ICECALv3");
    setId(0);

    add(Attrib::ELEMENT); add (Attrib::HARDWARE);
    debug("ICECALv3 built.","ICECALv3::ICECALv3");

    //Configuration register initilization:
    //Sub-address = 9.
    //#bytes = 3 (address + data<1> + data<0>).
    confReg=new Register();
    confReg->setName("ConfigRegister");
    confReg->io()->setSubAddress(9);    
    confReg->io()->defDataU8(3);    
    confReg->io()->setWordSize(IOdata::Byte);

    addChild(confReg);  
}

//Configuration file is read and parameters are applied to the electronics.
PyObject* ICECALv3::loadConfig(string configFile)
{
    string paramName[64];
    int paramValue[64], nParams;
    PyObject* asicParams;

    PyObject* fullConfiguration = PyList_New(0);
    //These are the names of the parameters that we are looking for in each case.
    string mainParams[] = {"VCONTROL_OE","BXID_SYN_OE","CLK_REFRESH","IBIAS_OB","IBIAS_CE_TH","IBIAS_TH","IBIAS_INT","IBIAS_CE_IN","IBIAS_CE_PZ","IBIAS_0T","IBIAS_PZ","IBIAS_V0T"};
    string analogParams[4][7]=      { {"CINT_SUBCH0[0]","CINT_SUBCH1[0]","IOFF_SUBCH0[0]","IOFF_SUBCH1[0]","ZERO[0]","POLE[0]","ZIN[0]"}
                                                                , {"CINT_SUBCH0[1]","CINT_SUBCH1[1]","IOFF_SUBCH0[1]","IOFF_SUBCH1[1]","ZERO[1]","POLE[1]","ZIN[1]"}
                                                                , {"CINT_SUBCH0[2]","CINT_SUBCH1[2]","IOFF_SUBCH0[2]","IOFF_SUBCH1[2]","ZERO[2]","POLE[2]","ZIN[2]"}
                                                                , {"CINT_SUBCH0[3]","CINT_SUBCH1[3]","IOFF_SUBCH0[3]","IOFF_SUBCH1[3]","ZERO[3]","POLE[3]","ZIN[3]"}             };
    string delayLineParams[4][5]= { {"PHASE_ADC[0]","PHASE_TH[0]","PHASE_INT[0]","LOC_SEL[0]","LVDS_OEN[0]"}
                                                                ,{"PHASE_ADC[1]","PHASE_TH[1]","PHASE_INT[1]","LOC_SEL[1]","LVDS_OEN[1]"}
                                                                ,{"PHASE_ADC[2]","PHASE_TH[2]","PHASE_INT[2]","LOC_SEL[2]","LVDS_OEN[2]"}
                                                                ,{"PHASE_ADC[3]","PHASE_TH[3]","PHASE_INT[3]","LOC_SEL[3]","LVDS_OEN[3]"}               };

    nParams = parseParameterList(configFile, paramName, paramValue);

    if(nParams != -1)
    {
        //At this point we have an array of parameter names (string) and an array of values (int).
        //We obtain the parameter values of the 'mainParams' array by searching on the C++ dictionary.
        asicParams = fillParams(mainParams,12,paramName,paramValue,nParams);
        setMainReg(asicParams);
        PyList_Append(fullConfiguration,asicParams);

        for(int iCh=0 ; iCh<4 ; iCh++)
        {
            asicParams = fillParams(analogParams[iCh],7,paramName,paramValue,nParams);          //Parameters of the analog channel.
            setAnalogCh(iCh,asicParams);
            PyList_Append(fullConfiguration,asicParams);
            asicParams = fillParams(delayLineParams[iCh],5,paramName,paramValue,nParams);       //Parameters of the delay line channel.
            setDelayLineCh(iCh,asicParams);     
            PyList_Append(fullConfiguration,asicParams);
        }
    }
    return fullConfiguration;
}

int ICECALv3::parseParameterList(string configFile, string paramName[64], int paramValue[64])
{
    int iParams = 0, eqPos;
    string line;    

    std::ifstream fd(configFile.c_str());
    if(!fd)                                 //File NOT OK.
    {
        error(configFile+" could not be opened.","ICECALv3::loadConfig");
        return -1;
  }
    else                                        //File OK.
    {
        while(!fd.eof())                                    
        {
            getline(fd,line);
            eqPos = line.find("=");
            if((eqPos != string::npos) && (line[0] != '#'))     //If current line contains "=" and DO NOT start with "#", is a good parameter.
            {
                paramName[iParams]  = line.substr(0,eqPos);                                                         //We store the parameter name
                paramValue[iParams] = atoi(line.substr(eqPos+1,string::npos).c_str());  //and the parameter value.
                iParams++;
            }
        }
        return iParams;
    }
}

//This function generates the Python list.
PyObject* ICECALv3::fillParams(string paramListRet[],int paramListLen,string paramName[64],int paramValue[64],int fileParamLen)
{
    int iParamFile;
    bool found;
    PyObject* asicParams = PyList_New(0);

    //For each of the parameters of the list...
    for(int iList=0 ; iList<paramListLen ; iList++)
    {
        iParamFile=0;
        found = false;
        //We look for the parameter name in the C++ dictionary.
        while(iParamFile < fileParamLen && !found)
        {
            if(paramName[iParamFile].find(paramListRet[iList]) != string::npos)
            {
                PyList_Append(asicParams, PyInt_FromLong(paramValue[iParamFile]));
                found = true;
            }
            iParamFile++;
        }
    }
    return asicParams;
}

//Configuration is dumped to a file.
StatusCode ICECALv3::dumpConfig(string configFile, PyObject* chipId)
{
    PyObject* asicParams = PyList_New(0);
    bool ok;

    //The first list item is the Chip Identifier.
    PyList_Append(asicParams, chipId);

    //Let's ask for the configuration to our chip.
    //Each function will return the corresponding parameter list
    //of that register.
    for(int i=0;i<4;i++)
    {
        PyList_Append(asicParams, getDelayLineCh(i) );
        PyList_Append(asicParams, getAnalogCh(i) );
    }
    PyList_Append(asicParams, getMainReg() );

    ok = writeAsicParams(configFile,asicParams);

    if(ok) return StatusCode::SUCCESS;
    else   return StatusCode::FAILURE;
}

bool ICECALv3::writeAsicParams(string fileName, PyObject* asicParams)
{
  time_t rawtime;
  struct tm * timeinfo;
    char dStr[64], tStr[64];
    ofstream fd;
    PyObject* l;        //Temporary list to accomodate 'asicParams' main list list objects.

    //'asicParams' output example:
    //['R1403C0000', [19, 24, 0, 0, 1], [2, 3, 6, 0, 0, 0, 19, 48, 0], [19, 24, 0, 0, 1],
    // [2, 3, 6, 0, 0, 0, 19, 48, 0], [19, 24, 0, 0, 1], [2, 3, 6, 0, 0, 0, 19, 48, 0], 
    // [19, 24, 0, 0, 1], [2, 3, 6, 0, 0, 0, 19, 48, 0], [0, 0, 0, 56, 0, 56, 0, 9, 56, 0, 56, 0]]

  time (&rawtime);
  timeinfo = localtime (&rawtime);
    strftime (dStr,64,"%Y/%m/%d",timeinfo);
    strftime (tStr,64,"%R",timeinfo);   

    fd.open (fileName.c_str(), ios_base::out);
    if(fd.is_open())
    {
        fd << "#########################################################" << endl;
        fd << "#############   ICECAL CALIBRATION FILE   ###############" << endl;
        fd << "#########################################################" << endl;
        fd << "" << endl;
        fd << "#File Version     : v" << CALIBRATION_FILE_VER << endl;
        fd << "#Date (YYYY/MM/DD): " << string(dStr) << endl;
        fd << "#Time (HH:MM)     : " << string(tStr) << endl;
        fd << "#ICECAL Chip ID   : " << PyString_AsString(PyList_GetItem(asicParams,0)) << endl;
        fd << "" << endl << endl;
    
        fd << "#########################################################" << endl;
        fd << "# ICECAL Main Register Parameters:" << endl;
        fd << "#########################################################" << endl;
        fd << "" << endl;

        l = PyList_GetItem(asicParams,9);       //list item 9. ICECAL Main config reg.
        fd <<   "VCONTROL_OE = " << PyInt_AsLong(PyList_GetItem(l,0)) << endl;
        fd <<   "BXID_SYN_OE = " << PyInt_AsLong(PyList_GetItem(l,1)) << endl;
        fd <<   "CLK_REFRESH = " << PyInt_AsLong(PyList_GetItem(l,2)) << endl;
        fd <<   "IBIAS_OB    = " << PyInt_AsLong(PyList_GetItem(l,3)) << endl;
        fd <<   "IBIAS_CE_TH = " << PyInt_AsLong(PyList_GetItem(l,4)) << endl;
        fd <<   "IBIAS_TH    = " << PyInt_AsLong(PyList_GetItem(l,5)) << endl;
        fd <<   "IBIAS_INT   = " << PyInt_AsLong(PyList_GetItem(l,6)) << endl;
        fd <<   "IBIAS_CE_IN = " << PyInt_AsLong(PyList_GetItem(l,7)) << endl;
        fd <<   "IBIAS_CE_PZ = " << PyInt_AsLong(PyList_GetItem(l,8)) << endl;  
        fd <<   "IBIAS_0T    = " << PyInt_AsLong(PyList_GetItem(l,9)) << endl;
        fd <<   "IBIAS_PZ    = " << PyInt_AsLong(PyList_GetItem(l,10)) << endl;
        fd <<   "IBIAS_V0T   = " << PyInt_AsLong(PyList_GetItem(l,11)) << endl;
        fd << "" << endl << endl;

        for(int i=0;i<4;i++)
        {
            fd << "#########################################################" << endl;
            fd << "#Channel #" << i << " Parameters:" << endl;
            fd << "#########################################################" << endl;
            fd << "" << endl;

            l = PyList_GetItem(asicParams,1+2*i);       //list items 1, 3, 5, 7. Delay line config regs.
            fd <<   "PHASE_ADC[" << i << "]   = " << PyInt_AsLong(PyList_GetItem(l,0)) << endl;
            fd <<   "PHASE_TH[" << i << "]    = " << PyInt_AsLong(PyList_GetItem(l,1)) << endl;
            fd <<   "PHASE_INT[" << i << "]   = " << PyInt_AsLong(PyList_GetItem(l,2)) << endl;
            fd <<   "LOC_SEL[" << i << "]     = " << PyInt_AsLong(PyList_GetItem(l,3)) << endl;
            fd <<   "LVDS_OEN[" << i << "]    = " << PyInt_AsLong(PyList_GetItem(l,4)) << endl;

            l = PyList_GetItem(asicParams,2+2*i);       //list items 2, 4, 6, 8. ICECAL Analog config regs.
            fd <<   "CINT_SUBCH0[" << i << "] = " << PyInt_AsLong(PyList_GetItem(l,0)) << endl;
            fd <<   "CINT_SUBCH1[" << i << "] = " << PyInt_AsLong(PyList_GetItem(l,1)) << endl;
            fd <<   "IOFF_SUBCH0[" << i << "] = " << PyInt_AsLong(PyList_GetItem(l,2)) << endl;
            fd <<   "IOFF_SUBCH1[" << i << "] = " << PyInt_AsLong(PyList_GetItem(l,3)) << endl;
            fd <<   "ZERO[" << i << "]        = " << PyInt_AsLong(PyList_GetItem(l,4)) << endl;
            fd <<   "POLE[" << i << "]        = " << PyInt_AsLong(PyList_GetItem(l,5)) << endl;
            fd <<   "ZIN[" << i << "]         = " << PyInt_AsLong(PyList_GetItem(l,6)) << endl; 
            fd << "" << endl;
        }

        fd.close();
        return true;
    }
    else return false;
}


//Verbosely commented code.
//Reads the delay line SPI register and returns all the values by means of a PyList of PyOject.
PyObject* ICECALv3::getDelayLineCh(int ch) 
{                            
    U8 spiAddr = delayLineAddrCh[ch];           //The SPI address of this delay line channel.
    U16 rxData = spiRead(spiAddr);              //rxData contains the 16 bits corresponding to the delay line channel.

    int phaseADC, phaseTH, phaseINT, locSel, lvdsOEn;
    PyObject* dllParams = PyList_New(0);

    if(err) PyList_Append(dllParams, PyInt_FromLong(-1));
    else
    {
        phaseADC = (rxData >> 11) & 0x1F;       //5 bits.
        phaseTH  = (rxData >> 6 ) & 0x1F;       //5 bits.
        phaseINT = (rxData >> 3 ) & 0x07;       //3 bits.
        locSel   = (rxData >> 1 ) & 0x03;       //2 bits.
        lvdsOEn  = (rxData & 0x01);                 //1 bit.

        //Converts integers to PyInt objects and then appends them to the PyList
        PyList_Append(dllParams, PyInt_FromLong(phaseADC));
        PyList_Append(dllParams, PyInt_FromLong(phaseTH));
        PyList_Append(dllParams, PyInt_FromLong(phaseINT));
        PyList_Append(dllParams, PyInt_FromLong(locSel));
        PyList_Append(dllParams, PyInt_FromLong(lvdsOEn));

        info("Delay Line Channel <"+itos(ch)+"> configuration (@SPI = 0x"+itohs(spiAddr)+"):","ICECALv3::getDelayLine");
        info("   ·Phase ADC          : "+itos(phaseADC),"ICECALv3::getDelayLine");
        info("   ·Phase T&H          : "+itos(phaseTH) ,"ICECALv3::getDelayLine");
        info("   ·Phase INT          : "+itos(phaseINT),"ICECALv3::getDelayLine");
        info("   ·LVDS Current Sel   : "+itos(locSel)  ,"ICECALv3::getDelayLine");
        info("   ·LVDS Output enable : "+itos(lvdsOEn) ,"ICECALv3::getDelayLine");
    }
    return dllParams;
}

//Reads the delay line SPI register and returns all the values by means of a PyList of PyOject.
StatusCode ICECALv3::setDelayLineCh(int ch, PyObject* dllParams) 
{                            
    U16 txData;
    int phaseADC, phaseTH, phaseINT, locSel, lvdsOEn;

    U8 spiAddr = delayLineAddrCh[ch];           //The SPI address of this delay line channel.

    //Converts the elements of the PyList to integers.
    phaseADC = PyInt_AsLong(PyList_GetItem(dllParams,0));
    phaseTH  = PyInt_AsLong(PyList_GetItem(dllParams,1));
    phaseINT = PyInt_AsLong(PyList_GetItem(dllParams,2));
    locSel   = PyInt_AsLong(PyList_GetItem(dllParams,3));
    lvdsOEn  = PyInt_AsLong(PyList_GetItem(dllParams,4));

    //txData contains the 16 bits corresponding to the delay line channel.
    txData =  ((phaseADC & 0x1F) << 11) | ((phaseTH & 0x1F) << 6) | ((phaseINT & 0x1F) << 3) | ((locSel & 0x03) << 1) | (lvdsOEn & 0x01);

    //Data is sent and checked. If there is a random write/read error, data is written again.
    err = spiWriteSafe(spiAddr,txData); 

    if(err) return StatusCode::FAILURE;
    else        return StatusCode::SUCCESS;
}


//Non-verbosely commented code. If you have questions, look at the code above.
PyObject* ICECALv3::getAnalogCh(int ch) 
{                            
    U8 spiLsbAddr = icecalLSBAddrCh[ch];            //The SPI address of the 16 LSBs.
    U8 spiMsbAddr = icecalMSBAddrCh[ch];            //The SPI address of the 16 MSBs.

    int cIntMsb, cIntLsb0, cIntLsb1, iOffMsb, cIntSubCh0, cIntSubCh1, iOffLsb0, iOffLsb1, iOffSubCh0, iOffSubCh1, zero, pole, zIn;
    PyObject* icecalChParams = PyList_New(0);

    //32 bit register from two SPI 16-bit registers.
    U32 rxData = (spiRead(spiMsbAddr) << 16) | spiRead(spiLsbAddr);

    if(err) PyList_Append(icecalChParams, PyInt_FromLong(-1));
    else
    {
        cIntMsb     = (rxData >> 30) & 0x03;        //2 bits.
        cIntLsb0    = (rxData >> 27) & 0x07;        //3 bits.
        cIntLsb1    = (rxData >> 24) & 0x07;        //3 bits.
        iOffMsb     = (rxData >> 20) & 0x0F;        //4 bits.
        iOffLsb0    = (rxData >> 18) & 0x03;        //2 bits.
        iOffLsb1    = (rxData >> 16) & 0x03;        //2 bits.
        zero            = (rxData >> 11) & 0x1F;        //5 bits.
        pole            = (rxData >> 5)  & 0x3F;        //6 bits.
        zIn             = (rxData)           & 0x1F;        //5 bits.

        cIntSubCh0 = (cIntMsb << 3) | cIntLsb0;     //cInt: The 2 MSB are shared between subchannels.
        cIntSubCh1 = (cIntMsb << 3) | cIntLsb1;     //The 3 LSB may differ from subchannels.
        iOffSubCh0 = (iOffMsb << 2) | iOffLsb0;     //iOff: 4 common + 2 different.
        iOffSubCh1 = (iOffMsb << 2) | iOffLsb1;

        PyList_Append(icecalChParams, PyInt_FromLong(cIntSubCh0));
        PyList_Append(icecalChParams, PyInt_FromLong(cIntSubCh1));
        PyList_Append(icecalChParams, PyInt_FromLong(iOffSubCh0));
        PyList_Append(icecalChParams, PyInt_FromLong(iOffSubCh1));
        PyList_Append(icecalChParams, PyInt_FromLong(zero));
        PyList_Append(icecalChParams, PyInt_FromLong(pole));
        PyList_Append(icecalChParams, PyInt_FromLong(zIn));

        info("ICECAL Analog Channel <"+itos(ch)+"> (MSB @SPI = 0x"+itohs(spiMsbAddr)+". LSB @SPI = 0x"+itohs(spiLsbAddr)+"):","ICECALv3::getIcecal");
        info("   ·Integrator capacitor SubCh<0> : "+itos(cIntSubCh0)    ,"ICECALv3::getAnalogCh");
        info("   ·Integrator capacitor SubCh<1> : "+itos(cIntSubCh1)    ,"ICECALv3::getAnalogCh");
        info("   ·Offset Current SubCh<0>       : "+itos(iOffSubCh0)    ,"ICECALv3::getAnalogCh");
        info("   ·Offset Current SubCh<1>       : "+itos(iOffSubCh1)    ,"ICECALv3::getAnalogCh");
        info("   ·PZ Zero capacitor             : "+itos(zero)              ,"ICECALv3::getAnalogCh");
        info("   ·PZ Pole capacitor             : "+itos(pole)              ,"ICECALv3::getAnalogCh");
        info("   ·Input impedance control       : "+itos(zIn)                   ,"ICECALv3::getAnalogCh");
    }
    return icecalChParams;
}

StatusCode ICECALv3::setAnalogCh(int ch, PyObject* icecalChParams) 
{                            
    U16 hTx, lTx;
    int cIntMsb, cIntLsb0, cIntLsb1, cIntSubCh0, cIntSubCh1, iOffMsb, iOffLsb0, iOffLsb1;
    int iOffSubCh0, iOffSubCh1, zero, pole, zIn;

    U8 spiLsbAddr = icecalLSBAddrCh[ch];            //The SPI address of the 16 LSBs.
    U8 spiMsbAddr = icecalMSBAddrCh[ch];            //The SPI address of the 16 MSBs.

    cIntSubCh0 = PyInt_AsLong(PyList_GetItem(icecalChParams,0));
    cIntSubCh1 = PyInt_AsLong(PyList_GetItem(icecalChParams,1));
    iOffSubCh0 = PyInt_AsLong(PyList_GetItem(icecalChParams,2));
    iOffSubCh1 = PyInt_AsLong(PyList_GetItem(icecalChParams,3));
    zero             = PyInt_AsLong(PyList_GetItem(icecalChParams,4));
    pole             = PyInt_AsLong(PyList_GetItem(icecalChParams,5));
    zIn              = PyInt_AsLong(PyList_GetItem(icecalChParams,6));

    //Integretor Capacitor and Offset current configuration registers share the MSBs between subchannels.
    //Therefore, these MSBs must be equal. Otherwise registers won't be properly configured. 
    if(((cIntSubCh0 & 0x18) == (cIntSubCh1 & 0x18)) && ((iOffSubCh0 & 0x3C) == (iOffSubCh1 & 0x3C)))
    {
        //Integretor capacitor: 2 + 3 bits.
        cIntMsb  = (cIntSubCh0 >> 3) & 0x3;
        cIntLsb0 =  cIntSubCh0 & 0x7;
        cIntLsb1 =  cIntSubCh1 & 0x7;
        //Offset current: 4 + 2 bits.
        iOffMsb  = (iOffSubCh0 >> 2) & 0xF;
        iOffLsb0 =  iOffSubCh0 & 0x3;
        iOffLsb1 =  iOffSubCh1 & 0x3;

        hTx =  ((cIntMsb & 0x3) << 14) | ((cIntLsb0 & 0x7) << 11) | ((cIntLsb1 & 0x7) << 8) | 
                     ((iOffMsb & 0xF) << 4)  | ((iOffLsb0 & 0x3) << 2)  | ((iOffLsb1 & 0x3));
        lTx =    ((zero & 0x1F) << 11)   | ((pole & 0x3F) << 5)     | (zIn & 0x1F);

                            err = spiWriteSafe(spiMsbAddr,hTx); 
        if(!err)    err = spiWriteSafe(spiLsbAddr,lTx);

        if(err) return StatusCode::FAILURE;
        else        return StatusCode::SUCCESS;
    }
    else 
    {
        if((cIntSubCh0 & 0x18) != (cIntSubCh1 & 0x18)) error("Integrator Cap MSB sub-channel mismatch. MSB<0> = "+itohs(cIntSubCh0)+", MSB<1> = "+itohs(cIntSubCh1)+".","ICECALv3::setAnalogCh");
        if((iOffSubCh0 & 0x3C) != (iOffSubCh1 & 0x3C)) error("Offset Current MSB sub-channel mismatch. MSB<0> = "+itohs(iOffSubCh0)+", MSB<1> = "+itohs(iOffSubCh1)+".","ICECALv3::setAnalogCh");
        return StatusCode::FAILURE;
    }
}


PyObject* ICECALv3::getMainReg() 
{                            
    U16 rxD[4];

    int vCtlOE, bxidSynOE, clkRefreshEn, iBiasOB, iBiasCETH, iBiasTH, iBiasINT;
    int iBiasCEINT, iBiasCEPZ, iBias0T, iBiasPZ, iBiasV0T;
    PyObject* icecalMainParams = PyList_New(0);

    for(int i=0;i<4;i++) rxD[i] = spiRead(icecalMainAddr[i]);       //4 registers of 16 bits.

    if(err) PyList_Append(icecalMainParams, PyInt_FromLong(-1));
    else
    {
        //Delay Line & Slow Control main configuration bits.
        vCtlOE              = !((rxD[3] >> 15) & 0x01);     //1 bit (active low) (d63).
        bxidSynOE           = !((rxD[3] >> 14) & 0x01);     //1 bit (active low) (d62).
        clkRefreshEn    = !((rxD[3] >> 13) & 0x01);     //1 bit (active low) (d61).

        //Bias currents for the analog channels.
        iBiasOB             = (rxD[3] >> 6) & 0x3F;     //6 bits (d59..54).
        iBiasCETH           = (rxD[3])          & 0x3F;     //6 bits (d53..48).
        iBiasTH             = (rxD[2] >> 6) & 0x3F;     //6 bits (d43..38).
        iBiasINT            = (rxD[2] )         & 0x3F;     //6 bits (d37..32).
        iBiasCEINT      =((rxD[1] >> 9) & 0x38) | ((rxD[0] >> 12) & 0x7);       //6 bits (d30..28, d14..12).
        iBiasCEPZ           = (rxD[1] >> 6) & 0x3F;     //6 bits (d27..22).
        iBias0T             = (rxD[1])          & 0x3F;     //6 bits (d21..16).
        iBiasPZ             = (rxD[0] >> 6) & 0x3F;     //6 bits (d11..06).
        iBiasV0T            = (rxD[0])          & 0x3F;     //6 bits (d05..00).

        PyList_Append(icecalMainParams, PyInt_FromLong(vCtlOE));
        PyList_Append(icecalMainParams, PyInt_FromLong(bxidSynOE));
        PyList_Append(icecalMainParams, PyInt_FromLong(clkRefreshEn));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasOB));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasCETH));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasTH));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasINT));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasCEINT));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasCEPZ));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBias0T));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasPZ));
        PyList_Append(icecalMainParams, PyInt_FromLong(iBiasV0T));

        info("ICECAL Main Register (@SPI = [0x"+itohs(icecalMainAddr[3])+"..0x"+itohs(icecalMainAddr[0])+"]):","ICECALv3::getIcecalMain");
        info("   ·DLL Control Voltage Output Enable: " + itos(vCtlOE)               ,"ICECALv3::getIcecalMain");
        info("   ·BXID Resynch Output Enable       : " + itos(bxidSynOE)        ,"ICECALv3::getIcecalMain");
        info("   ·SPI Clock refresh Enable         : " + itos(clkRefreshEn) ,"ICECALv3::getIcecalMain");
        info("   ·Output Buffer bias               : " + itos(iBiasOB)          ,"ICECALv3::getIcecalMain");
        info("   ·Track & Hold OpAmp bias (CE)     : " + itos(iBiasCETH)        ,"ICECALv3::getIcecalMain");
        info("   ·Track & Hold OpAmp bias          : " + itos(iBiasTH)          ,"ICECALv3::getIcecalMain");
        info("   ·Integrator OpAmp bias            : " + itos(iBiasINT)         ,"ICECALv3::getIcecalMain");
        info("   ·Integrator OpAmp bias (CE)       : " + itos(iBiasCEINT)       ,"ICECALv3::getIcecalMain");
        info("   ·Pole-Zero OpAmp bias (CE)        : " + itos(iBiasCEPZ)        ,"ICECALv3::getIcecalMain");
        info("   ·0T bias                    : " + itos(iBias0T)            ,"ICECALv3::getIcecalMain");
        info("   ·Pole-Zero OpAmp bias             : " + itos(iBiasPZ)          ,"ICECALv3::getIcecalMain");
        info("   ·0T bias (V0T)              : " + itos(iBiasV0T)           ,"ICECALv3::getIcecalMain");
    }
    return icecalMainParams;
}

StatusCode ICECALv3::setMainReg(PyObject* icecalMainParams) 
{                            
    U16 txD[4];

    int vCtlOE, bxidSynOE, clkRefreshEn, iBiasOB, iBiasCETH, iBiasTH, iBiasINT;
    int iBiasCEINT, iBiasCEPZ, iBias0T, iBiasPZ, iBiasV0T;
    
    vCtlOE              = !PyInt_AsLong(PyList_GetItem(icecalMainParams,0));    //Active low.
    bxidSynOE       = !PyInt_AsLong(PyList_GetItem(icecalMainParams,1));    //Active low.
    clkRefreshEn    = !PyInt_AsLong(PyList_GetItem(icecalMainParams,2));    //Active low.
    iBiasOB         = PyInt_AsLong(PyList_GetItem(icecalMainParams,3));
    iBiasCETH           = PyInt_AsLong(PyList_GetItem(icecalMainParams,4));
    iBiasTH             = PyInt_AsLong(PyList_GetItem(icecalMainParams,5));
    iBiasINT            = PyInt_AsLong(PyList_GetItem(icecalMainParams,6));
    iBiasCEINT      = PyInt_AsLong(PyList_GetItem(icecalMainParams,7));
    iBiasCEPZ       = PyInt_AsLong(PyList_GetItem(icecalMainParams,8));
    iBias0T             = PyInt_AsLong(PyList_GetItem(icecalMainParams,9));
    iBiasPZ             = PyInt_AsLong(PyList_GetItem(icecalMainParams,10));
    iBiasV0T        = PyInt_AsLong(PyList_GetItem(icecalMainParams,11));

    txD[3] = ((vCtlOE & 0x1) << 15)         | ((bxidSynOE & 0x1) << 14) | ((clkRefreshEn & 0x1) << 13) | ((iBiasOB & 0x3F) << 6) | (iBiasCETH & 0x3F);
    txD[2] = ((iBiasTH & 0x3F) << 6)        |  (iBiasINT  & 0x3F); 
    txD[1] = ((iBiasCEINT & 0x38) << 9) | ((iBiasCEPZ & 0x3F) << 6) |  (iBias0T      & 0x3F);
    txD[0] = ((iBiasCEINT & 0x7) << 12) | ((iBiasPZ   & 0x3F) << 6) |  (iBiasV0T     & 0x3F);

    //Four 16-bit registers are written.
    err = 0;
    for(int i=0;i<4;i++) err |= spiWriteSafe(icecalMainAddr[i],txD[i]);

    if(err) return StatusCode::FAILURE;
    else        return StatusCode::SUCCESS;
}


bool ICECALv3::spiWriteSafe(U8 confRegAddr, U16 confRegData)
{
    U16 rxRegData;
    bool ok = true;
    int iteration = 0;

    do{
        //Data is sent and read back...
        spiWrite(confRegAddr,confRegData);  
        rxRegData = spiRead(confRegAddr);

        //Exit conditions are computed.
        ok = (rxRegData == confRegData);
        iteration++;
    
        if(!ok) warning("Mismatch ("+itohs(iteration)+") in @SPI = 0x"+itohs(confRegAddr)+". Read: 0x"+itohs(rxRegData)+". Expected: 0x"+itohs(confRegAddr)+".","ICECALv3::spiWriteSafe"); 

    }while(!ok && iteration<= nRetries);

    if(!ok) error("Too many errors ("+itohs(iteration)+"). Check electronics!","ICECALv3::spiWriteSafe");
    return !ok;
}

//Basic reading operation...
U16 ICECALv3::spiRead(U8 confRegAddr, U8 offsetAddr)
{
    U16 rxData;

    U8* buffer = confReg->io()->dataU8();
    buffer[2]  = confRegAddr + offsetAddr;                          //+128 = read   

    if (confReg->read().isFailure()) 
    {
        warning("ICECALv3 read (@"+itohs(confRegAddr)+") error.","ICECALv3::spiRead");
        err = true;
        return 0;
    }
    else
    {
        err = false;
        rxData = ((U16)buffer[1] * 256) + (U16)buffer[0];
        debug("Register (@"+ itohs(confRegAddr) + ") = 0x" + itohs(rxData),"ICECALv3::spiRead");
        return rxData;
    }

}

//Basic writing operation...
void ICECALv3::spiWrite(U8 confRegAddr, U16 confRegData)
{
    U8* buffer = confReg->io()->dataU8();
    buffer[2] = confRegAddr;                                //Frame = buffer<2>, buffer<1>, buffer<0>
    buffer[1] = (confRegData >> 8) & 0xFF;
    buffer[0] =  confRegData       & 0xFF;

    err = confReg->write().isFailure();

    if(err)     warning("ICECALv3 write error.","ICECALv3::spiWrite");
    else      debug("ICECALv3 write (@"+ itohs(confRegAddr) + ") = 0x" + itohs(confRegData),"ICECALv3::spiWrite");
}

//                      SPI Slave FER Test                         //
PyObject* ICECALv3::spiFERTest(long nTest)
{
    long iTest, nBadTx=0, nBadRx=0, nFatal=0, nBad, regErrorHistogram[16];
    int iFrame, iRetry, readOk, writeOk;
    double fer;
    U16 writeData = 0x0000;
    U16 readData, retry;
    PyObject* ferStatistics         = PyList_New(0); 
    PyObject* confRegAddresses  = PyList_New(0);
    PyObject* confRegHistogram  = PyList_New(0);

    U8  addr;
    U8  confRegList[16] = {icecalMainAddr[0] , icecalMainAddr[1] , icecalMainAddr[2] , icecalMainAddr[3] , delayLineAddrCh[0] , delayLineAddrCh[1] , delayLineAddrCh[2] , delayLineAddrCh[3] ,
                                                 icecalLSBAddrCh[0], icecalLSBAddrCh[1], icecalLSBAddrCh[2], icecalLSBAddrCh[3], icecalMSBAddrCh[0] , icecalMSBAddrCh[1] , icecalMSBAddrCh[2] , icecalMSBAddrCh[3]};

    //Error histogram. This will compute the number of error in each register address.
    for(int i=0 ; i<16 ; i++) regErrorHistogram[i] = 0;

    info("Starting SPI FER test...","ICECALv3::spiFERTest");

    //FER Test is performed N Times
    for(iTest=0 ; iTest<nTest ; iTest++)
    {
        //For each test we check the 16 RW registers of the chip.
        for(iFrame=0 ; iFrame<16 ; iFrame++)
        {
            addr = confRegList[iFrame];

            //Random data to be sent.
            writeData = rand() + rand();

            //Write + Read back.    
            spiWrite(addr,writeData);
            readData = spiRead(addr);   

            //Data mismatch: let's see if it's a read, write or FATAL error;
            if(writeData != readData)
            {
                //The number of coincidences are counted. This loop will break when 5 R/W coincidences are found or after 50 retrials.
                iRetry = 0;     readOk = 0;         writeOk = 0;
                do
                {
                    retry = spiRead(addr);
                    if(retry == readData )  readOk++;
                    if(retry == writeData) writeOk++;
                    iRetry++;
                }
                while(readOk < 5 && writeOk < 5 && iRetry < 50);

                //Number of total errors according to the source.
                if          (iRetry >= 50) {    error("Mismatch: the source of the SPI error could not be determined","ICECALv3::spiFER");  nFatal++;   }
                else if (readOk >= 5)    {  error("Mismatch: Write error @SPI = 0x"+itohs(addr)+". W = 0x"+itohs(writeData)+", R = 0x"+itohs(readData)+".","ICECALv3::spiFER");     nBadTx++;   }
                else                                     {  error("Mismatch: Read error @SPI = 0x"+itohs(addr)+".  W = 0x"+itohs(writeData)+", R = 0x"+itohs(readData)+".","ICECALv3::spiFER");     nBadRx++;   }

                //Number of total errors according to the number of SPI register.
                regErrorHistogram[iFrame]++;
            }
        }
    }
    nBad = nFatal + nBadTx + nBadRx;                            //Global number of errors.
    fer = (double)nBad / ((double)nTest * 16.0);    //Frame Rate Error.

    for(iFrame=0 ; iFrame<16 ; iFrame++) PyList_Append(confRegAddresses, PyInt_FromLong(confRegList[iFrame]));              //A list with the SPI @s.
    for(iFrame=0 ; iFrame<16 ; iFrame++) PyList_Append(confRegHistogram, PyInt_FromLong(regErrorHistogram[iFrame]));    //The number of errors in this SPI @s.

    //FER statistics list:
    PyList_Append(ferStatistics, PyInt_FromLong(nBad));         //# Bad frames (global).
    PyList_Append(ferStatistics, PyFloat_FromDouble(fer));  //Global FER (0 ~ 1).
    PyList_Append(ferStatistics, PyInt_FromLong(nFatal));       //# Fatal frames.
    PyList_Append(ferStatistics, PyInt_FromLong(nBadTx));       //# Bad TX frames.
    PyList_Append(ferStatistics, PyInt_FromLong(nBadRx));       //# Bad RX frames.
    PyList_Append(ferStatistics, confRegAddresses);                 //SPI @ list.
    PyList_Append(ferStatistics, confRegHistogram);                 //SPI error counters list.

    warning("SPI BER test finished!!!");
    return ferStatistics;
}

void ICECALv3::reset(){

}

//Get version of the ICECAL Chip:
double ICECALv3::version()
{
    U16 rxversion;
    double major,minor,version;
    string version_str;

    rxversion = spiRead(ICECAL_VERSION_ADDR, 0x00 );

    major = (double)((rxversion>>12) & 0x0F); 
    minor = (double)((rxversion >>8) & 0x0F);
    version_str = itos(major) + "." + itos(minor);
    version = atof( version_str.c_str() );

    info("ICECAL Version: " + ftos(version),"ICECALv3::version");
    return version;
}

bool ICECALv3::bxidResynchStatus()
{
    U16 rxData;

    rxData = spiRead(BXID_RESYNCH_ADDR, 0x00 );

    info("RX = " + itohs(rxData),"");
    return(rxData > 127);

}

void ICECALv3::spiAddressScan()
{
    U16 rxData;
    unsigned int addr, rw, pumpRst, conf, regSel;

    for(addr=0; addr<256; addr++)
    {
        rw      = (addr>>7);
        pumpRst = (addr>>6) & 0x01;
        conf    = (addr>>5) & 0x01;
        regSel  = addr & 0x1F;

        rxData = spiRead( (U8) addr , 0x00 );
        warning("R/!W="+itos(rw)+" PUMPrst="+itos(pumpRst)+" !CONF/STAT="+itos(conf)+" REGsel="+itos(regSel)+" ~ SPI(@=0x"+itohs(addr)+") = 0x"+itohs(rxData),"ICECALv3::spiAddressScan");
    }
}