A3PE.cpp

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//------------------------------------------------------------------------------
//
//  Package    : A3PE
//
//  Description:
//
//  Author(s)  : F. Machefert -
//  Date       : 10 February 2004
//
//------------------------------------------------------------------------------
#include <iostream>
#include <sstream>
#include <fstream>

// include files
#ifndef WIN32
#include <unistd.h>
#endif
#include <algorithm>

// local include file
#include "A3PE.h"

// =====
// Resets register

StatusCode A3PE::resetStorageFifo(){
  info("Reset Storage Fifo","A3PE::resetStorageFifo");
  return m_resetReg->setBit(1,1);
}

StatusCode A3PE::resetUsbPhasers(){
  info("Reset USB Phasers","A3PE::resetUsbPhasers");
  return m_resetReg->setBit(2,1);
}

StatusCode A3PE::resetLatencyCounter(){
  info("Reset Latency counter","A3PE::resetLatencyCounter");
  return m_resetReg->setBit(4,1);
}

StatusCode A3PE::resetAcquisitionWriteCounter(){
  info("Reset acquisition write counter","A3PE::resetAcquisitionWriteCounter");
  return m_resetReg->setBit(5,1);
}

StatusCode A3PE::resetPatternFifo(){
  info("Reset Pattern Fifo","A3PE::resetPatternFifo");
  return m_resetReg->setBit(6,1);
}

StatusCode A3PE::resetTriggerFifo(){
  info("Reset Trigger Fifo","A3PE::resetTriggerFifo");
  return m_resetReg->setBit(7,1);
}

StatusCode A3PE::resetToAXRam(){
  info("Reset ToAx Ram","A3PE::resetToAXRam");
  return m_resetReg->setBit(8,1);
}

StatusCode A3PE::resetFromAXRam(){
  info("Reset FromAX Ram","A3PE::resetFromAXRam");
  return m_resetReg->setBit(9,1);
}

StatusCode A3PE::resetSequenceFromToAX(){
  info("Reset Sequence From-To AX","A3PE::resetSequenceFromToAX");
  return m_resetReg->setBit(10,1);
}

StatusCode A3PE::resetFE(){
  info("Reset FE triggered.","A3PE::resetFE");
  return m_resetReg->setBit(14,1);
}

StatusCode A3PE::resetSPI(){
  info("Reset SPI triggered.","A3PE::resetSPI");
  return m_resetReg->setBit(15,1);
}

// =====
// Setup Register

// Set

StatusCode A3PE::setEnableADC(unsigned int adc, bool enable){
  if (adc<8){
    info("Configuring ADC "+itos(adc)+" input enable to "+itos(enable));
    return m_setupReg->setBit(adc,enable);
  }
  else{
    warning("You cannot setup adc number "+itos(adc)+
        ". No action.","A3PE::setEnableADC");
    return StatusCode::FAILURE;
  }
}

StatusCode A3PE::setWriteStorageFifoUsb(bool enable){
  if (enable) {
    if (m_setupReg->setBit(8,true).isFailure()||
        m_setupReg->setBit(9,true).isFailure()){
      error("Cannot set usb storage fifo write bit","A3PE::setWriteStorageFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Storage Fifo Usb Write mode set.","A3PE::setWriteStorageFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
  else {
    if (m_setupReg->setBit(8,false).isFailure()||
        m_setupReg->setBit(9,false).isFailure()){
      error("Cannot set fifo storage ADC write bit","A3PE::setWriteStorageFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Storage Fifo ADC Write mode set.","A3PE::setWriteStorageFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
}

StatusCode A3PE::setReadPatternFifoUsb(bool enable){
  if (enable){
    if (m_setupReg->setBit(9,true).isFailure()){
      error("Cannot set pattern fifo read bit",
          "A3PE::setReadPatternFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Pattern Fifo Usb read mode set.",
           "A3PE::setReadPatternFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
  else {
    if (m_setupReg->setBit(9,false).isFailure()){
      error("Cannot set pattern fifo read bit",
          "A3PE::setReadPatternFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Pattern Fifo 40MHz read mode set.",
           "A3PE::setWritePatternFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
}


StatusCode A3PE::setReadTriggerFifoUsb(bool enable){
  if (enable){
    if (m_setupReg->setBit(11,true).isFailure()){
      error("Cannot set trigger fifo read bit",
          "A3PE::setReadtriggerFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Trigger Fifo Usb read mode set.",
           "A3PE::setReadTriggerFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
  else {
    if (m_setupReg->setBit(11,false).isFailure()){
      error("Cannot set trigger fifo read bit",
          "A3PE::setReadTriggerFifoUsb");
      return StatusCode::FAILURE;
    }
    else {
      info("Trigger Fifo 40MHz read mode set.",
           "A3PE::setReadTriggerFifoUsb");
    }
    return StatusCode::SUCCESS;
  }
}

StatusCode A3PE::setAddToAXRam(int add){
  m_toAXRamPtr->io()->setU16(0,(add&0x1FF));
  if (m_toAXRamPtr->write().isFailure()){
    error("Cannot write toAxRamPtr register "+m_toAXRamPtr->name(),
        "A3PE::setAddToAXRam");
    return StatusCode::FAILURE;
  }
  debug("toAXRamPtr register set to "+itos(add)+".","A3PE::setAddToAXRam");
  return StatusCode::SUCCESS;
}

StatusCode A3PE::setAddFromAXRam(int add){
  m_fromAXRamPtr->io()->setU16(0,(add&0x1FF));
  if (m_fromAXRamPtr->write().isFailure()){
      error("Cannot write AddFromAxRam register "+m_fromAXRamPtr->name(),
          "A3PE::setAddFromAXRam");
      return StatusCode::FAILURE;
  }
  debug("fromAXRamPtr register set to "+itos(add)+".","A3PE::setAddFromAXRam");
  return StatusCode::SUCCESS;
}

StatusCode A3PE::setReadToAXRamUsb(bool enable){
  if (m_setupReg->setBit(10,enable).isFailure()||
      m_setupReg->setBit(11,enable).isFailure()){
    error("Cannot set ToAXfifo read bit","A3PE::setReadToAXRamUsb");
    return StatusCode::FAILURE;
  }
  else {
    debug("ToAXRam read mode set.","A3PE::setReadToAXRamUsb");
  }
  return StatusCode::SUCCESS;
}

StatusCode A3PE::setWriteFromAXRamUsb(bool enable){
  if (m_setupReg->setBit(10,enable).isFailure()||
      m_setupReg->setBit(11,enable).isFailure()){
    error("Cannot set usb FromAXfifo write bit","A3PE::writeFromAXFifoUsb");
    return StatusCode::FAILURE;
  }
  else {
    debug("write FromAXFifo USB Write mode set.","A3PE::writeFromAXFifoUsb");
  }
  return StatusCode::SUCCESS;
}

StatusCode A3PE::setAXRamUsb(bool enable){
  if (enable) {
      if (m_setupReg->setBit(9,1).isFailure()||
          m_setupReg->setBit(11,1).isFailure()
          //||m_setupReg->setBit(12,0).isFailure()
          ){
          error("Cannot set AXRam USB clock mode","A3PE::setAXRamUsb");
          return StatusCode::FAILURE;
      }
  }
  else {
      if (m_setupReg->setBit(9,0).isFailure()||
          m_setupReg->setBit(11,0).isFailure()
          //||m_setupReg->setBit(12,1).isFailure()
          ){
        error("Cannot set AXRam acquisition clock mode","A3PE::setAXRamUsb");
        return StatusCode::FAILURE;
      }
  }
  debug("AXRam USB clock mode set to "+itos(enable),"A3PE::setAXRamUsb");
  return StatusCode::SUCCESS;
}

bool A3PE::writeStorageFifoUsb(){
  if (m_setupReg->getBit(8)==1&&m_setupReg->getBit(9)==1) return true;
  return false;
}

bool A3PE::readPatternFifoUsb(){
  if (m_setupReg->getBit(9)==1) return true;
  return false;
}

bool A3PE::readTriggerFifoUsb(){
  if (m_setupReg->getBit(9)==1) return true;
  return false;
}

// Get

bool A3PE::enableADC(unsigned int adc){
  if (adc<8){
    return m_setupReg->getBit(adc);
  }
  return false;
}

bool A3PE::readToAXRamUsb(){
  return (m_setupReg->getBit(10)==1&&m_setupReg->getBit(11)==1);
}

bool A3PE::writeFromAXRamUsb(){
  return (m_setupReg->getBit(10)==1&&m_setupReg->getBit(11)==1);
}

StatusCode A3PE::setInternalAXSequence(bool mode){
  info("Switch AX internal loop mode to "+itos(mode),"A3PE::setInternalAXSequence");
  return m_setupReg->setBit(12,mode);
}

bool A3PE::internalAXSequence(){
  debug("Get fpga loop mode","A3PE::internalAXSequence");
  return m_setupReg->getBit(12);
}

StatusCode A3PE::setPipeline(unsigned int val){
  if (val>2) {
    warning("Cannot set pipeline to coded value "+itos(val),"A3PE::setPipeline");
    return StatusCode::FAILURE;
  }
  m_acqReg->read();
  unsigned int data=(m_acqReg->io()->dataU16()[0])&0xFF3F;
  m_acqReg->io()->setU16(0,data|(((val&3)<<6)));
  if (m_acqReg->write().isFailure()){
    error("Cannot write acquisition register "+m_acqReg->name(),
      "A3PE::setPipeline");
    return StatusCode::FAILURE;
  }
  info("Acquisition register bits set to "+itos(val),"A3PE::setPipeline");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::pipeline(){
  if (m_acqReg->read().isFailure()){
    error("Cannot read acquisition register "+m_acqReg->name(),
      "A3PE::pipeline");
    return 0;
  }
  return (((m_acqReg->io()->dataU16()[0])>>6)&3);
}

StatusCode A3PE::setLengthAX(unsigned int val){
  m_lengthAX->io()->setU16(0,val&0xfff);
  if (m_lengthAX->write().isFailure()){
    error("Cannot write length AX register "+m_lengthAX->name(),
        "Register::setLengthAX");
    return StatusCode::FAILURE;
  }
  debug("LengthAX register set to "+itos(val),"A3PE::setLengthAX");
  return StatusCode::SUCCESS;
}

StatusCode A3PE::setLatencyAX(unsigned int val){
  m_latencyAX->io()->setU32(0,val);
  if (m_latencyAX->write().isFailure()){
    error("Cannot write latency AX register "+m_latencyAX->name(),
        "Register::setLatencyAX");
    return StatusCode::FAILURE;
  }
  debug("LatencyAX register set to "+itos(val),"A3PE::setLatencyAX");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::lengthAX(){
  if (m_lengthAX->read().isFailure()){
    error("Cannot read Length AX register "+m_lengthAX->name(),
        "A3PE::lengthAX");
    return 0;
  }
  unsigned long int data=m_lengthAX->io()->dataU16()[0];
  return (data&0xffff);
}

unsigned int A3PE::latencyAX(){
  if (m_latencyAX->read().isFailure()){
    error("Cannot read Latency AX register "+m_latencyAX->name(),
        "A3PE::latencyAX");
    return 0;
  }
  unsigned long int data=m_latencyAX->io()->dataU32()[0];
  return (data&0xffffff);
  return 0;
}


// =====
// Acquisition register

StatusCode A3PE::trigger(){
  debug("Trigger sequence started","A3PE::trigger");
  return m_acqReg->setBit(0,1);
}

StatusCode A3PE::setSoftwareTrigger(bool enable){
  if (m_acqReg->setBit(1,enable).isFailure()){
    error("Cannot set software trigger bit","A3PE::setSoftwareTrigger");
    return StatusCode::FAILURE;
  }
  else{
    info("Software trigger mode set to "+itos(enable),"A3PE::setSoftwareTrigger");
  }
  return StatusCode::SUCCESS;
}

bool A3PE::softwareTrigger(){
  return m_acqReg->getBit(1);
}

StatusCode A3PE::enableStorage(){
  // enable data storage
  if (m_acqReg->read().isFailure()){
    error("Cannot read acquisition register "+name(),"A3P3::enableStorage");
    return StatusCode::FAILURE;
  }
  unsigned int data=m_acqReg->io()->dataU16()[0];
  //  info("Value before acquisition: "+itos(data));
  data|=4;
  m_acqReg->io()->setU16(0,data);
  if (m_acqReg->write().isFailure()){
    error("Cannot write acquisition register ","A3P3::enableStorage");
    return StatusCode::FAILURE;
  }
  // reset the busy line
  m_resetReg->io()->setU16(0,8);
  if (m_resetReg->write().isFailure()){
    error("Cannot reset Busy line"+name(),"A3P3::enableStorage");
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;
}

bool A3PE::dataReady(){
  bool isReady=m_acqReg->getBit(2);
  if (isReady) {
    debug("Spying EnableStorage bit - Data Ready: NO ","A3PE::dataReady");
  }
  else {
    debug("Spying EnableStorage bit - Data Ready: YES","A3PE::dataReady");
  }
  return (!isReady);
}

StatusCode A3PE::acquisition(){
  debug("Acquisition sequence started","A3PE::acquisition");
  warning("This acquisition trigger does not release the busy bit !",
      "A3PE::acquisition");
  return m_acqReg->setBit(3,1);
}

// =====
// Status register

// =====
// Clock division register
StatusCode A3PE::setClockDivision(unsigned int val){
  if (m_clockDivisionReg->read().isFailure()){
    error("Cannot read Clock Division register "+m_clockDivisionReg->name(),
        "Register::setClockDivision");
    return StatusCode::FAILURE;
  }
  unsigned long int data=m_clockDivisionReg->io()->dataU32()[0];
  data &= ~(16777215); // switch last 24 bits at 0
  data |= ( val & 16777215 );   // or with the desired value
  m_clockDivisionReg->io()->setU32(0,data);
  if (m_clockDivisionReg->write().isFailure()){
    error("Cannot write Clock Division register "+m_clockDivisionReg->name(),
        "Register::setClockDivision");
    return StatusCode::FAILURE;
  }
  info("Clock Division set to "+itos(val),"A3PE::setClockDivision");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::clockDivision(){
  if (m_clockDivisionReg->read().isFailure()){
    error("Cannot read Clock Division register "+m_clockDivisionReg->name(),
        "Register::setClockDivision");
    return 0;
  }
  unsigned long int data=m_clockDivisionReg->io()->dataU32()[0];
  return (data&(16777215)); // switch last 24 bits at 0
}

// ======
// Trigger generator
 
StatusCode A3PE::setTriggerDelay(unsigned int val){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::setTriggerDelay");
    return StatusCode::FAILURE;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  data &= ~(255); // switch last 8 bits to 0
  data |= ( val & 255);   // or with the desired value
  m_triggerReg->io()->setU32(0,data);
  if (m_triggerReg->write().isFailure()){
    error("Cannot write Trigger register "+m_triggerReg->name(),
        "Register::setTriggerDelay");
    return StatusCode::FAILURE;
  }
  info("Trigger delay set to "+itos(val),"A3PE::setTriggerDelay");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::triggerDelay(){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::triggerDelay");
    return 0;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  return (data&(255));
}
/*
StatusCode A3PE::setSeqPulseDelay(unsigned int val){
  if (m_seqPulseReg->read().isFailure()){
    error("Cannot read SeqPulse register "+m_seqPulseReg->name(),
        "Register::setSeqPulseDelay");
    return StatusCode::FAILURE;
  }
  unsigned long int data=m_seqPulseReg->io()->dataU32()[0];
  data &= ~(255); // switch last 8 bits to 0
  data |= ( val & 255);   // or with the desired value
  m_seqPulseReg->io()->setU32(0,data);
  if (m_seqPulseReg->write().isFailure()){
    error("Cannot write seqPulse register "+m_seqPulseReg->name(),
        "Register::setSeqPulseDelay");
    return StatusCode::FAILURE;
  }
  info("SeqPulse delay set to "+itos(val),"A3PE::setSeqPulseDelay");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::seqPulseDelay(){
  if (m_seqPulseReg->read().isFailure()){
    error("Cannot read SeqPulse register "+m_seqPulseReg->name(),
        "Register::seqPulseDelay");
    return 0;
  }
  unsigned long int data=m_seqPulseReg->io()->dataU32()[0];
  return (data&(255));
}
*/

StatusCode A3PE::setTriggerRate(unsigned int val){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::setTriggerRate");
    return StatusCode::FAILURE;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  data &= ~(65535<<8); // switch 16 bits to 0
  data |= ( (val & 65535)<<8);   // or with the desired value
  m_triggerReg->io()->setU32(0,data);
  if (m_triggerReg->write().isFailure()){
    error("Cannot write Trigger register "+m_triggerReg->name(),
        "Register::setTriggerRate");
    return StatusCode::FAILURE;
  }
  info("Trigger rate set to "+itos(val),"A3PE::setTriggerRate");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::triggerRate(){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::setTriggerRate");
    return 0;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  return (data>>8) & (65535) ; 
}

StatusCode A3PE::setNTrigger(unsigned int val){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::setNTrigger");
    return StatusCode::FAILURE;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  data &= ~(255<<24); // switch last 8 bits at 0
  data |= (( val & 255)<<24);  // or with the desired value
  m_triggerReg->io()->setU32(0,data);
  if (m_triggerReg->write().isFailure()){
    error("Cannot write Trigger register "+m_triggerReg->name(),
        "Register::setNTrigger");
    return StatusCode::FAILURE;
  }
  info("Trigger counter set to "+itos(val),"A3PE::setNTrigger");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::nTrigger(){
  if (m_triggerReg->read().isFailure()){
    error("Cannot read Trigger register "+m_triggerReg->name(),
        "Register::setNTrigger");
    return 0;
  }
  unsigned long int data=m_triggerReg->io()->dataU32()[0];
  return ((data>>24)&255);
}

// =====
// Latency register

StatusCode A3PE::setFifoLatency(unsigned short val){
  if (m_latencyReg->read().isFailure()){
    error("Cannot read Latency register "+m_latencyReg->name(),
        "Register::setFifoLatency");
    return StatusCode::FAILURE;
  }
  unsigned short data=m_latencyReg->io()->dataU16()[0];
  data = (val & 65535);   
  m_latencyReg->io()->setU16(0,data);
  if (m_latencyReg->write().isFailure()){
    error("Cannot write Latency register "+m_latencyReg->name(),
        "Register::setFifoLatency");
    return StatusCode::FAILURE;
  }
  info("Trigger Fifo Latency set to "+itos(val),"Register::setFifoLatency");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::fifoLatency(){
  if (m_latencyReg->read().isFailure()){
    error("Cannot read Latency register "+m_latencyReg->name(),
        "Register::setFifoLatency");
    return 0;
  }
  unsigned short data=m_latencyReg->io()->dataU16()[0];
  return (data&65535);   
}

// =====
// Fifo depth

StatusCode A3PE::setFifoDepth(unsigned int val){
  if (m_writeLengthFifoReg->read().isFailure()){
    error("Cannot read writeLengthFifo register "+m_writeLengthFifoReg->name(),
        "Register::setFifoDepth");
    return StatusCode::FAILURE;
    m_storageRam->setSize(96,val);
  }
  unsigned short data=m_writeLengthFifoReg->io()->dataU16()[0];
  data = (val & 511);   
  m_writeLengthFifoReg->io()->setU16(0,data);
  if (m_writeLengthFifoReg->write().isFailure()){
    error("Cannot write writeLengthFifo register "+m_writeLengthFifoReg->name(),
        "Register::setFifoDepth");
    return StatusCode::FAILURE;
  }
  info("Fifo Depth set to "+itos(val),"Register::setFifoDepth");
  return StatusCode::SUCCESS;
}

unsigned int A3PE::fifoDepth(){
  if (m_writeLengthFifoReg->read().isFailure()){
    error("Cannot read writeLengthFifo register "+m_writeLengthFifoReg->name(),
        "Register::setFifoDepth");
    return 0;
  }
  unsigned short data=m_writeLengthFifoReg->io()->dataU16()[0];
  return (data&511);   
}

void A3PE::dumpStorage(){
  RAM* fifo=storageRam();
  fifo->read();
  int val[12];
  char line[100];
  for (unsigned int d=0; d<fifoDepth(); ++d){
    val[0] =fifo->io()->dataU8( 0+12*d);
    val[1] =fifo->io()->dataU8( 1+12*d);
    val[2] =fifo->io()->dataU8( 2+12*d);
    val[3] =fifo->io()->dataU8( 3+12*d);
    val[4] =fifo->io()->dataU8( 4+12*d);
    val[5] =fifo->io()->dataU8( 5+12*d);
    val[6] =fifo->io()->dataU8( 6+12*d);
    val[7] =fifo->io()->dataU8( 7+12*d);
    val[8] =fifo->io()->dataU8( 8+12*d);
    val[9] =fifo->io()->dataU8( 9+12*d);
    val[10]=fifo->io()->dataU8(10+12*d);
    val[11]=fifo->io()->dataU8(11+12*d);
    sprintf(line,"%3d -> %4d %4d %4d %4d %4d %4d %4d %4d",
        d,
        val[0]+((val[1]&0xf)<<8),(val[1]>>4)+(val[2]<<4),
        val[3]+((val[4]&0xf)<<8),(val[4]>>4)+(val[5]<<4),
        val[6]+((val[7]&0xf)<<8),(val[7]>>4)+(val[8]<<4),
        val[9]+((val[10]&0xf)<<8),(val[10]>>4)+(val[11]<<4)
        );
    info(line);
  }
}

void A3PE::loadStorage(std::string filename){
  std::ifstream ifs(filename.c_str(),std::ifstream::in);
  std::string s;
  std::string comment;
  std::istringstream instream;
  U8* data=storageRam()->io()->dataU8();
  int depth=fifoDepth();
  int d=0;
  int c0, c1, c2, c3, c4, c5, c6, c7;
  while (getline(ifs, s) && d<depth) { // Reads line into s
      instream.clear();     // Reset from possible previous errors.
      instream.str(s);      // Use s as source of input.
      instream>>std::ws;
      if (!instream.eof()) {
        instream >> comment;
        if (comment==std::string("#")) {
          info(s);
        }
        else {
          instream.clear();     // Reset from possible previous errors.
          instream.str(s);      // Use s as source of input.
          instream>>c0>>c1>>c2>>c3>>c4>>c5>>c6>>c7;
          info(itos(c0)+" "+itos(c1)+" "+itos(c2)+" "+itos(c3)
              +" "+itos(c4)+" "+itos(c5)+" "+itos(c6)+" "+itos(c7));
          data[   12*d]=(c0&0xff);
          data[ 1+12*d]=((c0>>8)&0xf)+((c1<<4)&0xf0);
          data[ 2+12*d]=((c1>>4)&0xff);
          data[ 3+12*d]=(c2&0xff);
          data[ 4+12*d]=((c2>>8)&0xf)+((c3<<4)&0xf0);
          data[ 5+12*d]=((c3>>4)&0xff);
          data[ 6+12*d]=(c4&0xff);
          data[ 7+12*d]=((c4>>8)&0xf)+((c5<<4)&0xf0);
          data[ 8+12*d]=((c5>>4)&0xff);
          data[ 9+12*d]=(c6&0xff);
          data[10+12*d]=((c6>>8)&0xf)+((c7<<4)&0xf0);
          data[11+12*d]=((c7>>4)&0xff);
          d++;
        }
      }
  }
  ifs.close();
  setWriteStorageFifoUsb(true);
  storageRam()->write();
  setWriteStorageFifoUsb(false);
}

void A3PE::dumpPattern(){
  RAM* fifo=patternRam();
  setReadPatternFifoUsb(true);
  fifo->read();
  setReadPatternFifoUsb(false);
  int val[12];
  char line[100];
  for (unsigned int d=0; d<fifo->depth(); ++d){
    val[0] =fifo->io()->dataU8( 0+12*d);
    val[1] =fifo->io()->dataU8( 1+12*d);
    val[2] =fifo->io()->dataU8( 2+12*d);
    val[3] =fifo->io()->dataU8( 3+12*d);
    val[4] =fifo->io()->dataU8( 4+12*d);
    val[5] =fifo->io()->dataU8( 5+12*d);
    val[6] =fifo->io()->dataU8( 6+12*d);
    val[7] =fifo->io()->dataU8( 7+12*d);
    val[8] =fifo->io()->dataU8( 8+12*d);
    val[9] =fifo->io()->dataU8( 9+12*d);
    val[10]=fifo->io()->dataU8(10+12*d);
    val[11]=fifo->io()->dataU8(11+12*d);
    sprintf(line,"%3d -> %4d %4d %4d %4d %4d %4d %4d %4d",
        d,
        val[0]+((val[1]&0xf)<<8),(val[1]>>4)+(val[2]<<4),
        val[3]+((val[4]&0xf)<<8),(val[4]>>4)+(val[5]<<4),
        val[6]+((val[7]&0xf)<<8),(val[7]>>4)+(val[8]<<4),
        val[9]+((val[10]&0xf)<<8),(val[10]>>4)+(val[11]<<4)
        );
    info(line);
  }
}

void A3PE::loadPattern(std::string filename){
  std::ifstream ifs(filename.c_str(),std::ifstream::in);
  std::string s;
  std::string comment;
  std::istringstream instream;
  U8* data=patternRam()->io()->dataU8();
  int depth=patternRam()->depth();
  int d=0;
  int c0, c1, c2, c3, c4, c5, c6, c7;
  while (getline(ifs, s) && d<depth) { // Reads line into s
      instream.clear();     // Reset from possible previous errors.
      instream.str(s);      // Use s as source of input.
      instream>>std::ws;
      if (!instream.eof()) {
        instream >> comment;
        if (comment==std::string("#")) {
          info(s);
        }
        else {
          instream.clear();     // Reset from possible previous errors.
          instream.str(s);      // Use s as source of input.
          instream>>c0>>c1>>c2>>c3>>c4>>c5>>c6>>c7;
          info(itos(c0)+" "+itos(c1)+" "+itos(c2)+" "+itos(c3)
              +" "+itos(c4)+" "+itos(c5)+" "+itos(c6)+" "+itos(c7));
          data[   12*d]=(c0&0xff);
          data[ 1+12*d]=((c0>>8)&0xf)+((c1<<4)&0xf0);
          data[ 2+12*d]=((c1>>4)&0xff);
          data[ 3+12*d]=(c2&0xff);
          data[ 4+12*d]=((c2>>8)&0xf)+((c3<<4)&0xf0);
          data[ 5+12*d]=((c3>>4)&0xff);
          data[ 6+12*d]=(c4&0xff);
          data[ 7+12*d]=((c4>>8)&0xf)+((c5<<4)&0xf0);
          data[ 8+12*d]=((c5>>4)&0xff);
          data[ 9+12*d]=(c6&0xff);
          data[10+12*d]=((c6>>8)&0xf)+((c7<<4)&0xf0);
          data[11+12*d]=((c7>>4)&0xff);
          d++;
        }
      }
  }
  ifs.close();
  patternRam()->write();
}

void A3PE::dumpTrigger(){
  RAM* fifo=triggerRam();
  setReadTriggerFifoUsb(true);
  fifo->read();
  setReadTriggerFifoUsb(false);
  int val;
  char line[100];
  for (int d=0; d<fifo->depth(); ++d){
    val=fifo->io()->dataU8(d);
    sprintf(line,"%3d -> %1d %1d %1d %1d %1d %1d %1d %1d",
        d,
        val&0x1,(val>>1)&0x1,(val>>2)&0x1,(val>>3)&0x1,
        (val>>4)&0x1,(val>>5)&0x1,(val>>6)&0x1,(val>>7)&0x1);
    info(line);
  }
}


void A3PE::loadTrigger(std::string filename){
  std::ifstream ifs(filename.c_str(),std::ifstream::in);
  std::string s;
  std::string comment;
  std::istringstream instream;
  U8* data=triggerRam()->io()->dataU8();
  int depth=triggerRam()->depth();
  int d=0;
  int c0, c1, c2, c3, c4, c5, c6, c7;
  while (getline(ifs, s) && d<depth) { // Reads line into s
      instream.clear();     // Reset from possible previous errors.
      instream.str(s);      // Use s as source of input.
      instream>>std::ws;
      if (!instream.eof()) {
        instream >> comment;
        if (comment==std::string("#")) {
          info(s);
        }
        else {
          instream.clear();     // Reset from possible previous errors.
          instream.str(s);      // Use s as source of input.
          instream>>c0>>c1>>c2>>c3>>c4>>c5>>c6>>c7;
          info(itos(c0)+" "+itos(c1)+" "+itos(c2)+" "+itos(c3)
              +" "+itos(c4)+" "+itos(c5)+" "+itos(c6)+" "+itos(c7));
          data[d]=c0+((c1&0x1)<<1)+((c2&0x1)<<2)+((c3&0x1)<<3)+
              ((c4&0x1)<<4)+((c5&0x1)<<5)+((c6&0x1)<<6)+((c7&0x1)<<7);
          warning(itos(d)+" => "+itos(data[d]));
          d++;
        }
      }
  }
  ifs.close();
  triggerRam()->write();
}

void A3PE::dumpToAX(){
  setAddToAXRam(0);
  setReadToAXRamUsb(true);
  toAXRam()->read();
  setReadToAXRamUsb(false);
  U8* val=toAXRam()->io()->dataU8();
  char line[100];
  for (int d=0; d<toAXRam()->depth(); ++d){
    sprintf(line,"%3d -> %1d %1d %1d %1d",
        d,val[4*d],val[1+4*d],val[2+4*d],val[3+4*d]);
    info(line);
  }
}

void A3PE::loadToAX(std::string filename){
  setAXRamUsb(true);
  setAddToAXRam(0);
  info("loadtoax="+filename);
  std::ifstream ifs(filename.c_str(),std::ifstream::in);
  std::string s;
  std::string comment;
  std::istringstream instream;
  U8* data=toAXRam()->io()->dataU8();
  int depth=toAXRam()->depth();
  int d=0;
  int c0, c1, c2, c3;
  while (getline(ifs, s) && d<depth) { // Reads line into s
      instream.clear();     // Reset from possible previous errors.
      instream.str(s);      // Use s as source of input.
      instream>>std::ws;
      if (!instream.eof()) {
        instream >> comment;
        if (comment==std::string("#")) {
          info(s);
        }
        else {
          instream.clear();     // Reset from possible previous errors.
          instream.str(s);      // Use s as source of input.
          instream>>c0>>c1>>c2>>c3;
          info(itos(c0)+" "+itos(c1)+" "+itos(c2)+" "+itos(c3));
          data[  4*d]=c0&0xff;
          data[1+4*d]=c1&0xff;
          data[2+4*d]=c2&0xff;
          data[3+4*d]=c3&0xff;
          d++;
        }
      }
  }
  ifs.close();
  toAXRam()->write();
}

void A3PE::dumpFromAX(){
  setAXRamUsb(true);
  setAddFromAXRam(0);
  fromAXRam()->read();
  U8* val=fromAXRam()->io()->dataU8();
  unsigned int l=lengthAX();
  info("Length AX="+itos(l));
  char line[100];
  for (int d=0; d<l+2; ++d){
    sprintf(line,"%3d -> %1d %1d %1d %1d",
        d,val[4*d],val[1+4*d],val[2+4*d],val[3+4*d]);
    info(line);
  }
}

void A3PE::loadFromAX(std::string filename){
  setAddFromAXRam(0);
  std::ifstream ifs(filename.c_str(),std::ifstream::in);
  std::string s;
  std::string comment;
  std::istringstream instream;
  U8* data=fromAXRam()->io()->dataU8();
  int depth=fromAXRam()->depth();
  int d=0;
  int c0, c1, c2, c3;
  while (getline(ifs, s) && d<depth) { // Reads line into s
      instream.clear();     // Reset from possible previous errors.
      instream.str(s);      // Use s as source of input.
      instream>>std::ws;
      if (!instream.eof()) {
        instream >> comment;
        if (comment==std::string("#")) {
          info(s);
        }
        else {
          instream.clear();     // Reset from possible previous errors.
          instream.str(s);      // Use s as source of input.
          instream>>c0>>c1>>c2>>c3;
          info(itos(c0)+" "+itos(c1)+" "+itos(c2)+" "+itos(c3));
          data[  4*d]=c0&0xff;
          data[1+4*d]=c1&0xff;
          data[2+4*d]=c2&0xff;
          data[3+4*d]=c3&0xff;
          d++;
        }
      }
  }
  ifs.close();
  setWriteFromAXRamUsb(true);
  fromAXRam()->write();
  setWriteFromAXRamUsb(false);
}

StatusCode A3PE::startSequenceAX(){
  setAXRamUsb(false);
  setAddToAXRam(0);
  setAddFromAXRam(0);
  if (m_acqReg->setBit(4,1).isFailure()){
    error("Cannot set AX sequence start bit bit","A3PE::startAXSequence");
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;
}