A3PE.h

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//$Id: A3PE.h,v 1.3 2006/09/28 13:02:23 fmachefe Exp $
//------------------------------------------------------------------------------
//
//  Package    : A3PE
//
//  Description:
//
//  Author(s)  : F. Machefert -
//  Date       : 10 February 2004
//
//------------------------------------------------------------------------------

#ifndef __A3PE_H_
#define __A3PE_H_

#include "Element.h"
#include "RAM.h"
#include "Register.h"

class A3PE : public Element {
public:
  typedef unsigned long  U32;
  typedef unsigned short U16;
  typedef unsigned char  U8;
  A3PE(){
    setType("A3PE");
    setId(0);
    add(Attrib::ELEMENT); add (Attrib::HARDWARE);
    debug("A3PE built.","A3PE::A3PE");

    m_globalUsbReset=new Register();
    addChild(m_globalUsbReset);
    m_globalUsbReset->setName("GlobalUsbReset");
    m_globalUsbReset->io()->defDataU32(1);
    m_globalUsbReset->setAddress(112);

    m_ctrlReg=new Register();
    addChild(m_ctrlReg);
    m_ctrlReg->setName("CtrlRegister");
    m_ctrlReg->io()->defDataU32(1);
    m_ctrlReg->setAddress(20);

    m_resetReg=new Register();
    addChild(m_resetReg);
    m_resetReg->setName("ResetRegister");
    m_resetReg->io()->defDataU16(1);
    m_resetReg->setAddress(1);

    m_statusReg=new Register();
    addChild(m_statusReg);
    m_statusReg->setName("StatusRegister");
    m_statusReg->io()->defDataU16(1);
    m_statusReg->setAddress(3);

    m_setupReg=new Register();
    addChild(m_setupReg);
    m_setupReg->setName("SetupRegister");
    m_setupReg->io()->defDataU16(1);
    m_setupReg->setAddress(2);

    m_acqReg=new Register();
    addChild(m_acqReg);
    m_acqReg->setName("AcqRegister");
    m_acqReg->io()->defDataU16(1);
    m_acqReg->setAddress(4);

    m_latencyReg=new Register();
    addChild(m_latencyReg);
    m_latencyReg->setName("LatencyRegister");
    m_latencyReg->io()->defDataU16(1);
    m_latencyReg->setAddress(7);

    m_writeLengthFifoReg=new Register();
    addChild(m_writeLengthFifoReg);
    m_writeLengthFifoReg->setName("WriteLengthFifoRegister");
    m_writeLengthFifoReg->io()->defDataU16(1);
    m_writeLengthFifoReg->setAddress(8);

    //ICECAL Analog Mezzanine Relays:
    m_ctrlAnaMezzReg=new Register();
    addChild(m_ctrlAnaMezzReg);
    m_ctrlAnaMezzReg->setName("CtrlAnaMezzReg");
    m_ctrlAnaMezzReg->io()->defDataU32(1);
    m_ctrlAnaMezzReg->setAddress(20);

    m_clockDivisionReg=new Register();
    addChild(m_clockDivisionReg);
    m_clockDivisionReg->setName("ClockDivisionReg");
    m_clockDivisionReg->io()->defDataU32(1);
    m_clockDivisionReg->setAddress(23);

    m_triggerReg=new Register();
    addChild(m_triggerReg);
    m_triggerReg->setName("TriggerReg");
    m_triggerReg->io()->defDataU32(1);
    m_triggerReg->setAddress(24);

    m_toAXReg=new Register();
    addChild(m_toAXReg);
    m_toAXReg->setName("ToAXReg");
    m_toAXReg->io()->defDataU32(1);
    m_toAXReg->setAddress(26);

    m_fromAXReg=new Register();
    addChild(m_fromAXReg);
    m_fromAXReg->setName("FromAXReg");
    m_fromAXReg->io()->defDataU32(1);
    m_fromAXReg->setAddress(27);

    m_spare3Reg=new Register();
    addChild(m_spare3Reg);
    m_spare3Reg->setName("Spare3Reg");
    m_spare3Reg->io()->defDataU32(1);
    m_spare3Reg->setAddress(19);

    m_storageRam=new RAM();
    addChild(m_storageRam);
    m_storageRam->setName("StorageRam");
    m_storageRam->setSize(96,512);
    m_storageRam->setAddress(6);

    m_patternRam=new RAM();
    addChild(m_patternRam);
    m_patternRam->setName("PatternRam");
    m_patternRam->setSize(96,512);
    m_patternRam->setAddress(28);

    m_triggerRam=new RAM();
    addChild(m_triggerRam);
    m_triggerRam->setName("TriggerRam");
    m_triggerRam->setSize(8,512);
    m_triggerRam->setAddress(31);

    m_toAXRamPtr=new Register();
    addChild(m_toAXRamPtr);
    m_toAXRamPtr->setName("ToAXRamPtr");
    m_toAXRamPtr->io()->defDataU16(1);
    m_toAXRamPtr->setAddress(35);

    m_toAXRam=new RAM();
    addChild(m_toAXRam);
    m_toAXRam->setName("ToAXRam");
    m_toAXRam->setSize(32,512);
    m_toAXRam->setAddress(29);

    m_fromAXRamPtr=new Register();
    addChild(m_fromAXRamPtr);
    m_fromAXRamPtr->setName("FromAXRamPtr");
    m_fromAXRamPtr->io()->defDataU16(1);
    m_fromAXRamPtr->setAddress(36);

    m_fromAXRam=new RAM();
    addChild(m_fromAXRam);
    m_fromAXRam->setName("FromAXRam");
    m_fromAXRam->setSize(32,512);
    m_fromAXRam->setAddress(30);

    m_latencyAX=new Register();
    addChild(m_latencyAX);
    m_latencyAX->setName("LatencyAX");
    m_latencyAX->io()->defDataU32(1);
    m_latencyAX->setAddress(32);

    m_lengthAX=new Register();
    addChild(m_lengthAX);
    m_lengthAX->setName("LengthAX");
    m_lengthAX->io()->defDataU16(1);
    m_lengthAX->setAddress(34);

    m_testRam=new RAM();
    addChild(m_testRam);
    m_testRam->setName("TestRam");
    m_testRam->setSize(32,50);
    m_testRam->setAddress(27);
  }

  ~A3PE(){
    /*
    delete m_globalUsbReset;
    delete m_ctrlReg;
    delete m_resetReg;
    delete m_setupReg;
    delete m_statusReg;
    delete m_acqReg;
    delete m_latencyReg;
    delete m_writeLengthFifoReg;
    delete m_clockDivisionReg;
    delete m_triggerReg;
    delete m_toAXReg;
    delete m_fromAXReg;
    delete m_spare3Reg;
    delete m_storageRam;
    delete m_patternRam;
    delete m_triggerRam;
    delete m_toAXRam;
    delete m_fromAXRam;
    delete m_toAXRamPtr;
    delete m_fromAXRamPtr;
    delete m_lengthAX;
    delete m_latencyAX;
    delete m_testRam;
    */
  }

  void help() { info("A3PE "+name()+". No help.","A3PE::help"); };

  StatusCode init() {
    return StatusCode::SUCCESS;
  };

  void reset() {
        info("A3PE reset procedure.");
    info("A3PE global usb reset.","A3PE::reset");
    if (m_globalUsbReset->write().isFailure()){
      error("Cannot trigger a Global Usb reset on A3PE "+name(),"A3PE::reset");
    }
    info("A3PE global reset.","A3PE::reset");
        m_resetReg->io()->setU16(0,0xFFFF);
    if (m_resetReg->write().isFailure()){
      error("Cannot trigger a Global reset on A3PE "+name(),"A3PE::reset");
    }
  };

  StatusCode resetStorageFifo();

  StatusCode resetUsbPhasers();

  StatusCode resetLatencyCounter();

  StatusCode resetAcquisitionWriteCounter();

  StatusCode resetPatternFifo();

  StatusCode resetTriggerFifo();

  StatusCode resetToAXRam();

  StatusCode resetFromAXRam();

  StatusCode resetSequenceFromToAX();

  StatusCode resetFE();

  StatusCode resetSPI();

  StatusCode setEnableADC(unsigned int,bool);

  StatusCode setWriteStorageFifoUsb(bool);

  bool enableADC(unsigned int);

  bool writeStorageFifoUsb();

  StatusCode setReadPatternFifoUsb(bool);

  bool readPatternFifoUsb();

  StatusCode setReadTriggerFifoUsb(bool);

  bool readTriggerFifoUsb();

  StatusCode setReadToAXRamUsb(bool);

  bool readToAXRamUsb();

  StatusCode setWriteFromAXRamUsb(bool);

  bool writeFromAXRamUsb();

  StatusCode setAXRamUsb(bool);

  StatusCode startSequenceAX();

  StatusCode setSoftwareTrigger(bool);

  bool softwareTrigger();

  StatusCode setClockDivision(unsigned int);

  StatusCode setTriggerDelay(unsigned int);

  StatusCode setSeqPulseDelay(unsigned int);

  StatusCode setTriggerRate(unsigned int);

  StatusCode setNTrigger(unsigned int);

  StatusCode setFifoLatency(unsigned short);

  StatusCode setFifoDepth(unsigned int);

  unsigned int clockDivision();

  unsigned int triggerDelay();

  unsigned int seqPulseDelay();

  unsigned int triggerRate();

  unsigned int nTrigger();

  unsigned int fifoLatency();
  unsigned int fifoDepth();

  StatusCode acquisition();

  StatusCode enableStorage();

  StatusCode trigger();

  bool dataReady();

  void update () {
  };

  StatusCode setInternalAXSequence(bool);

  bool internalAXSequence();

  StatusCode setLengthAX(unsigned int);

  unsigned int lengthAX();

  StatusCode setLatencyAX(unsigned int);

  unsigned int latencyAX();

  StatusCode setPipeline(unsigned int);

  unsigned int pipeline();

  Register* ctrlReg(){
    return m_ctrlReg;
  }

  Register* setupReg(){
    return m_setupReg;
  }

  Register* resetReg(){
    return m_resetReg;
  }

  Register* statusReg(){
    return m_statusReg;
  }

  Register* acqReg(){
    return m_acqReg;
  }

  Register* latencyReg(){
    return m_latencyReg;
  }

  Register* writeLengthFifoReg(){
    return m_writeLengthFifoReg;
  }

  Register* ctrlAnaMezzReg(){
    return m_ctrlAnaMezzReg;
  }

  Register* clockDivisionReg(){
    return m_clockDivisionReg;
  }

  Register* triggerReg(){
    return m_triggerReg;
  }

  Register* toAXReg(){
    return m_toAXReg;
  }

  Register* fromAXReg(){
    return m_fromAXReg;
  }

  Register* spare3Reg(){
    return m_spare3Reg;
  }

  RAM* storageRam(){
    return m_storageRam;
  }

  RAM* patternRam(){
    return m_patternRam;
  }

  RAM* triggerRam(){
    return m_triggerRam;
  }

  RAM* toAXRam(){
    return m_toAXRam;
  }

  RAM* fromAXRam(){
    return m_fromAXRam;
  }

  RAM* testRam(){
    return m_testRam;
  }

  Register* fromAXRamPtrReg(){
    return m_fromAXRamPtr;
  }

  Register* toAXRamPtrReg(){
    return m_toAXRamPtr;
  }

  void dumpStorage();
  void loadStorage(std::string);

  void dumpPattern();
  void loadPattern(std::string);

  void dumpTrigger();
  void loadTrigger(std::string);

  void dumpToAX();
  void loadToAX(std::string);

  void dumpFromAX();
  void loadFromAX(std::string);

  StatusCode setAddToAXRam(int);
  StatusCode setAddFromAXRam(int);

private:
  Register*       m_globalUsbReset;
  Register*       m_ctrlReg;
  Register*       m_resetReg;
  Register*       m_setupReg;
  Register*       m_statusReg;
  Register*       m_acqReg;
  Register*       m_latencyReg;
  Register*       m_writeLengthFifoReg;
  Register*       m_ctrlAnaMezzReg;
  Register*       m_clockDivisionReg;
  Register*       m_triggerReg;
  Register*       m_toAXReg;
  Register*       m_fromAXReg;
  Register*       m_spare3Reg;
  RAM*            m_storageRam;
  RAM*            m_patternRam;
  RAM*            m_triggerRam;
  Register*       m_toAXRamPtr;
  Register*       m_fromAXRamPtr;
  RAM*            m_toAXRam;
  RAM*            m_fromAXRam;
  Register*       m_latencyAX;
  Register*       m_lengthAX;
  RAM*            m_testRam;
};

#endif