Cat
FePGA.cpp
Go to the documentation of this file.
1 //------------------------------------------------------------------------------
2 //
3 // Package : FePGA
4 //
5 // Description:
6 //
7 // Author(s) : F. Machefert - Yasmine Amhis
8 // Date : 10 February 2004 -- Modified 09-2017
9 //
10 //------------------------------------------------------------------------------
11 #include <iostream>
12 #include <sstream>
13 #include <fstream>
14 
15 // include files #Is this needed ?
16 #ifndef WIN32
17 #include <unistd.h>
18 #endif
19 #include <algorithm>
20 
21 // local include file
22 #include "FePGA.h"
23 
24 
25 //=============================================================================
26 // Standard constructor, initializes variables
27 //=============================================================================
28 
29 FePGA::FePGA(): m_addSpiReg() {
30  setType("FePGA");
31  setId(0);
32  add(Attrib::ELEMENT); add (Attrib::HARDWARE);
33  debug("FePGA built.","FePGA::FePGA");
34 
35  m_usb = new UsbFTMLInterface();
36  m_usb->setName("Usb");
37  addChild(m_usb);
38 
39  m_setupReg = MakeRegister("SetupReg", 0x01);
40  m_resetReg = MakeRegister("ResetReg", 0x02);
41  m_addSpiReg = MakeRegister("AddSpiReg", 0x03);
42  m_transmitSpiReg = MakeRegister("TransmitSpiReg", 0x0B);
43  m_ctrlSpiReg = MakeRegister("CtrlSpiReg", 0x0E);
44 
45  m_rxSpiFifo = MakeRAM("RxSpiFifo", 0x0C);
46  m_txSpiFifo = MakeRAM("TxSpiFifo", 0x0D);
47 
48  m_testFifo = MakeRAM("TestFifo", 0x05);
49 
50 }
51 
52 Register* FePGA::MakeRegister(std::string name, unsigned int add){
53 
54  Register* reg = new Register();
55  reg ->setName(name);
56  reg ->io()->defDataU8(2);
57  reg ->io()->setAddress(add);
58  reg ->io()->setWordSize(IOdata::Byte);
59  m_usb ->addChild(reg);
60 
61  return reg;
62 
63 }
64 
65 RAM* FePGA::MakeRAM(std::string name, unsigned int add){
66 
67  RAM* ram = new RAM();
68  ram ->setName(name);
69  ram ->setSize(16, 1024);
70  ram ->io()->setAddress(add);
71  m_usb ->addChild(ram);
72 
73  return ram;
74 
75 }
76 
77 StatusCode FePGA::setSpiAdd( unsigned long int value ){
78  m_addSpiReg->io()->setU8(0,value&0xFF);
79  m_addSpiReg->io()->setU8(1,(value>>8) & 0xFF);
80  return m_addSpiReg->write();
81 }
82 
83 
84 StatusCode FePGA::spiWrite(unsigned int subadd, unsigned int nwords, unsigned int *values){
85  // mode block pour write les mots dans un vecteur values
86 
87  unsigned int val = subadd & 0x7F;
88  m_txSpiFifo->setSize(16,nwords+1);
89  m_ctrlSpiReg->io()->setU8(0,nwords&0xFF);
90  m_ctrlSpiReg->io()->setU8(1,(nwords>>8)&0xFF);
91  m_ctrlSpiReg->write();
92  m_txSpiFifo->io()->setU8(0,val);
93  m_txSpiFifo->io()->setU8(1,0);
94  for (int w=0; w<nwords; ++w) {
95  m_txSpiFifo->io()->setU8(2*w+2,values[w]&0xFF);
96  m_txSpiFifo->io()->setU8(2*w+3,(values[w]>>8)&0xFF);
97  }
98  m_txSpiFifo->write();
99  return m_transmitSpiReg->write();
100 }
101 
102 StatusCode FePGA::spiRead (unsigned int subadd, unsigned int nwords, unsigned int *values) {
103  // mode block pour read les mots dans un vecteur values
104 
105  unsigned int val = subadd | 0x80 ;
106  m_txSpiFifo->setSize(16,1);
107  m_rxSpiFifo->setSize(16,nwords+1);
108  m_ctrlSpiReg->io()->setU8(0,(nwords+1)&0xFF);
109  m_ctrlSpiReg->io()->setU8(1,((nwords+1)>>8)&0xFF);
110  m_ctrlSpiReg->write();
111  m_txSpiFifo->io()->setU8(0,val);
112  m_txSpiFifo->io()->setU8(1,0);
113  m_txSpiFifo->write();
114  StatusCode status = m_transmitSpiReg->write();
115  // usleep(100000);
116  m_rxSpiFifo->read();
117  for (int w=0; w<nwords; ++w) {
118  values[w]=((m_rxSpiFifo->io()->dataU8(2*w+2))&0xFF)+
119  (((m_rxSpiFifo->io()->dataU8(2*w+3))&0xFF)<<8);
120  }
121  return status;
122 }
123 
124 StatusCode FePGA::spiWrite(unsigned int subadd, unsigned int nwords, PyObject* value){
125  unsigned int val = subadd & 0x7F;
126  m_txSpiFifo->setSize(16,nwords+1);
127  m_ctrlSpiReg->io()->setU8(0,nwords&0xFF);
128  m_ctrlSpiReg->io()->setU8(1,(nwords>>8)&0xFF);
129  m_ctrlSpiReg->write();
130  // m_ctrlSpiReg->read();
131  // m_ctrlSpiReg->dump();
132  m_txSpiFifo->io()->setU8(0,val);
133  m_txSpiFifo->io()->setU8(1,0);
134  for (int w=0; w<nwords; ++w) {
135  val = PyInt_AsLong(PyList_GetItem(value,w));
136  m_txSpiFifo->io()->setU8(2*w+2,val&0xFF);
137  m_txSpiFifo->io()->setU8(2*w+3,(val>>8)&0xFF);
138  }
139  // m_txSpiFifo->dump();
140  m_txSpiFifo->write();
141  return m_transmitSpiReg->write();
142 }
143 
144 PyObject* FePGA::spiRead (unsigned int subadd, unsigned int nwords) {
145  unsigned int val = subadd | 0x80 ;
146  m_txSpiFifo->setSize(16,1);
147  m_rxSpiFifo->setSize(16,nwords+1);
148  m_ctrlSpiReg->io()->setU8(0,(nwords+1)&0xFF);
149  m_ctrlSpiReg->io()->setU8(1,((nwords+1)>>8)&0xFF);
150  m_ctrlSpiReg->write();
151  // m_ctrlSpiReg->read();
152  // m_ctrlSpiReg->dump();
153  m_txSpiFifo->io()->setU8(0,val);
154  m_txSpiFifo->io()->setU8(1,0);
155  m_txSpiFifo->write();
156  StatusCode status = m_transmitSpiReg->write();
157  // usleep(100000);
158  m_rxSpiFifo->read();
159  PyObject* values = PyList_New(0);
160  for (int w=0; w<nwords; ++w) {
161  // m_rxSpiFifo->dump();
162  PyList_Append(values,
163  PyInt_FromLong( (long int) (
164  ((m_rxSpiFifo->io()->dataU8(2*w+2))&0xFF) +
165  (((m_rxSpiFifo->io()->dataU8(2*w+3))&0xFF)<<8)
166  )));
167  }
168  return values;
169 }
170 
171 StatusCode FePGA::spiWrite(unsigned int subadd, unsigned int value){
172  unsigned int val = subadd & 0x7F;
173  m_txSpiFifo->setSize(16,2);
174  m_ctrlSpiReg->io()->setU8(0,1);
175  m_ctrlSpiReg->io()->setU8(1,0);
176  m_ctrlSpiReg->write();
177  // m_ctrlSpiReg->read();
178  m_txSpiFifo->io()->setU8(0,val);
179  m_txSpiFifo->io()->setU8(1,0);
180  m_txSpiFifo->io()->setU8(2,value&0xFF);
181  m_txSpiFifo->io()->setU8(3,(value>>8)&0xFF);
182  m_txSpiFifo->write();
183  // m_txSpiFifo->dump();
184  return m_transmitSpiReg->write();
185 }
186 
187 unsigned int FePGA::spiRead (unsigned int subadd){
188  unsigned int val = subadd | 0x80 ;
189  m_txSpiFifo->setSize(16,1);
190  m_rxSpiFifo->setSize(16,1);
191  m_ctrlSpiReg->io()->setU8(0,1);
192  m_ctrlSpiReg->io()->setU8(1,0);
193  m_ctrlSpiReg->write();
194  m_txSpiFifo->io()->setU8(0,val);
195  m_txSpiFifo->io()->setU8(1,0);
196  m_txSpiFifo->write();
197  // m_txSpiFifo->dump();
198  StatusCode status = m_transmitSpiReg->write();
199  // usleep(100000);
200  m_rxSpiFifo->read();
201  // m_rxSpiFifo->dump();
202  return ((m_rxSpiFifo->io()->dataU8(0))&0xFF) + (((m_rxSpiFifo->io()->dataU8(1))&0xFF)<<8);
203 }
204 
205 //===============================================
206 
207 //=============================================================================
208 //
209 //=============================================================================
210 
211 StatusCode FePGA::setSpiGBTSCA( bool value ){
212  m_setupReg->read();
213  unsigned int data=m_setupReg->io()->dataU8()[0];
214  if (!value) data |= 2 ;
215  else data &= ~2 ;
216  m_setupReg->io()->setU8(0,data);
217  return m_setupReg->write();
218 }
219 
220 bool FePGA::spiGBTSCA( ){
221  m_setupReg->read();
222  return (! ( m_setupReg->io()->dataU8(0) & 2 ) ) ;
223 }
224 //=============================================================================
225 //
226 //=============================================================================
227 
228 StatusCode FePGA::setSpiSubAdd( unsigned long int value ){
229  m_spiSubAdd = value & 0x7F; //WARNING !!!! What Values to put here ??
230 }
231 
232 unsigned long int FePGA::spiSubAdd(){
233  return ( m_spiSubAdd ) ;
234 }
235 
236 //=============================================================================
237 //
238 
239 
240 
241 
242 
243 //===================================================================================
244 /*
245 
246 StatusCode FePGA::spiWrite(unsigned int subadd, unsigned int nwords, unsigned int *values){
247  unsigned int val = subadd & 0x7F; //WARNING !!!! What Values to put here ??
248 
249  m_fifo_test ->setSize(16, nwords +1 ); // ajouter le 25-09
250  m_fifo_test->io()->setU8(0,val); // ajoute le 25-09
251  m_fifo_test->io()->setU8(1,0); //ajouter le 25-09
252  m_fifo_test-> write(); // ajouter le 25-09
253  return m_transmitSpiReg->write();
254 
255  // m_txSpiFifo->setSize(16,nwords+1); //WARNING !!!! What Values to put here ??
256  //m_ctrlSpiReg->io()->setU8(0,nwords&0xFF); //WARNING !!!! What Values to put here ??
257  // m_ctrlSpiReg->io()->setU8(1,(nwords>>8)&0xFF); //WARNING !!!! What Values to put here ??
258  //m_ctrlSpiReg->write();
259 
260 
261 
262  //m_txSpiFifo->io()->setU8(0,val); //WARNING !!!! What Values to put here ??
263  //m_txSpiFifo->io()->setU8(1,0); //WARNING !!!! What Values to put here ??
264 
265 
266  // for (int w=0; w<nwords; ++w) {
267  // m_txSpiFifo->io()->setU8(2*w+2,values[w]&0xFF); //WARNING !!!! What Values to put here ??
268  // m_txSpiFifo->io()->setU8(2*w+3,(values[w]>>8)&0xFF); //WARNING !!!! What Values to put here ??
269  // }
270  // m_txSpiFifo->write();
271 
272 }
273 //===================================================================================
274 
275 PyObject* FePGA::spiRead (unsigned int subadd, unsigned int nwords) {
276  unsigned int val = subadd | 0x80 ; //WARNING !!!! What Values to put here ??
277 
278 
279  m_fifo_test->setSize(16,1); // ajoute le 25-09
280 
281  m_fifo_test->io()->setU8(0,val); // ajoute le 25-09
282  m_fifo_test->io()->setU8(1,0); // ajouter le 25-09
283  m_fifo_test->write(); //ajouter le 25-09
284 
285 
286 
287  m_txSpiFifo->setSize(16,1); //WARNING !!!! What Values to put here ??
288 
289  m_rxSpiFifo->setSize(16,nwords+1); //WARNING !!!! What Values to put here ??
290 
291 
292  m_ctrlSpiReg->io()->setU8(0,(nwords+1)&0xFF); //WARNING !!!! What Values to put here ??
293  m_ctrlSpiReg->io()->setU8(1,((nwords+1)>>8)&0xFF); //WARNING !!!! What Values to put here ??
294  m_ctrlSpiReg->write();
295 
296 
297  m_txSpiFifo->io()->setU8(0,val);//WARNING !!!! What Values to put here ??
298  m_txSpiFifo->io()->setU8(1,0); //WARNING !!!! What Values to put here ??
299  m_txSpiFifo->write();
300  StatusCode status = m_transmitSpiReg->write();
301 
302 
303  m_rxSpiFifo->read();
304  PyObject* values = PyList_New(0);
305  for (int w=0; w<nwords; ++w) {
306 
307  PyList_Append(values,
308  PyInt_FromLong( (long int) (
309  ((m_rxSpiFifo->io()->dataU8(2*w+2))&0xFF) +
310  (((m_rxSpiFifo->io()->dataU8(2*w+3))&0xFF)<<8)
311  )));//WARNING !!!! What Values to put here ??
312  }
313  return values;
314 }
315 
316 
317 
318 //=======================================================================
319 StatusCode FePGA::spiWrite(unsigned int subadd, unsigned int value){
320  unsigned int val = subadd & 0x7F; //WARNING !!!! What Values to put here ??
321  m_txSpiFifo->setSize(16,2); //WARNING !!!! What Values to put here ??
322  m_ctrlSpiReg->io()->setU8(0,1); //WARNING !!!! What Values to put here ??
323  m_ctrlSpiReg->io()->setU8(1,0); //WARNING !!!! What Values to put here ??
324  m_ctrlSpiReg->write();
325 
326  m_txSpiFifo->io()->setU8(0,val); //WARNING !!!! What Values to put here ??
327  m_txSpiFifo->io()->setU8(1,0); //WARNING !!!! What Values to put here ??
328  m_txSpiFifo->io()->setU8(2,value&0xFF); //WARNING !!!! What Values to put here ??
329  m_txSpiFifo->io()->setU8(3,(value>>8)&0xFF); //WARNING !!!! What Values to put here ??
330  m_txSpiFifo->write();
331 
332  return m_transmitSpiReg->write();
333 }
334 
335 //=======================================================================
336 
337 
338 unsigned int FePGA::spiRead (unsigned int subadd){
339  unsigned int val = subadd | 0x80 ; //WARNING !!!! What Values to put here ??
340  m_txSpiFifo->setSize(16,1); //WARNING !!!! What Values to put here ??
341  m_rxSpiFifo->setSize(16,1); //WARNING !!!! What Values to put here ??
342  m_ctrlSpiReg->io()->setU8(0,1); //WARNING !!!! What Values to put here ??
343  m_ctrlSpiReg->io()->setU8(1,0); //WARNING !!!! What Values to put here ??
344  m_ctrlSpiReg->write();
345  m_txSpiFifo->io()->setU8(0,val);//WARNING !!!! What Values to put here ??
346  m_txSpiFifo->io()->setU8(1,0);//WARNING !!!! What Values to put here ??
347  m_txSpiFifo->write();
348  // m_txSpiFifo->dump();
349  StatusCode status = m_transmitSpiReg->write();
350  // usleep(100000);
351  m_rxSpiFifo->read();
352  // m_rxSpiFifo->dump();
353  return ((m_rxSpiFifo->io()->dataU8(0))&0xFF) + (((m_rxSpiFifo->io()->dataU8(1))&0xFF)<<8);
354 //WARNING !!!! What Values to put here ??
355 }
356 
357 
358 */
359 
360 //=============================================================================
361 
362 StatusCode FePGA::setI2cGBTSCA( bool value ){
363  m_setupReg->read();
364  unsigned int data=m_setupReg->io()->dataU8()[0];
365  if (!value) data |= 1 ;
366  else data &= ~1 ;
367  m_setupReg->io()->setU8(0,data);
368  return m_setupReg->write();
369 }
370 
371 bool FePGA::i2cGBTSCA( ){
372  m_setupReg->read();
373  return (! ( m_setupReg->io()->dataU8(0) & 1 ) ) ;
374 }
375 
376 //=============================================================================
377 //=============================================================================
378 
379 StatusCode FePGA::setI2cBuffer( unsigned long int value ){
380  m_i2cBuffer = value;
381  return StatusCode::SUCCESS;
382 }
383 
384 unsigned long int FePGA::i2cBuffer(){
385  return m_i2cBuffer;
386 }
387 
388 //=============================================================================
389 //
390 //=============================================================================
391 unsigned long int FePGA::i2cData(){
392  return ( ((m_masterI2cReg->io()->dataU8(0))&0xFF) ) ; //WARNING !!!! What Values to put here ??
393 }
394 
395 //=============================================================================
396 //=============================================================================
397 
398 StatusCode FePGA::setI2cAdd( unsigned long int value ){
399  m_addI2cReg->io()->setU8(0,value&0xFF); //WARNING !!!! What Values to put here ??
400  m_addI2cReg->io()->setU8(1,(value&0xFF00)>>8); //WARNING !!!! What Values to put here ??
401  return m_addI2cReg->write();
402 }
403 //=============================================================================
404 unsigned long int FePGA::i2cAdd(){
405  m_addI2cReg->read();
406  return ( m_addI2cReg->io()->dataU8(0) + (m_addI2cReg->io()->dataU8(1)<<8) ) ; //WARNING !!!! What Values to put here ??
407 }
408 //=============================================================================
409 //
410 //=============================================================================
411 
412 StatusCode FePGA::setI2cSubAdd( unsigned long int value ){
413  m_i2cSubAdd = value;
414  return StatusCode::SUCCESS;
415 }
416 
417 unsigned long int FePGA::i2cSubAdd(){
418  return m_i2cSubAdd;
419 }
420 
421 //=============================================================================
422 //
423 //=============================================================================
424 //
425 //=============================================================================
426 
427 StatusCode FePGA::i2cRead( ){
428  debug("setting position of read i2c protocol","i2c read");
429  m_setupReg->read();
430  unsigned int data = m_setupReg->io()->dataU8()[0];//WARNING !!!! What Values to put here ??
431  data |= (1 << 2) ;
432  m_setupReg->io()->setU8(0,data);
433  m_setupReg->write();
434 
435  debug("setting subadd value in the frame","i2c write");
436  m_masterI2cReg->io()->defDataU8(2);
437  m_masterI2cReg->io()->setU8(0,m_i2cSubAdd&0xFF);//WARNING !!!! What Values to put here ??
438  m_masterI2cReg->io()->setU8(1,(m_i2cSubAdd>>8)&0xFF);//WARNING !!!! What Values to put here ??
439 
440  debug("i2c write of the register","i2c read");
441  m_masterI2cReg->write();
442 
443  debug("i2c read of the addressed register","i2c read");
444  m_masterI2cReg->io()->defDataU8(1);//WARNING !!!! What Values to put here ??
445  m_masterI2cReg->read();
446 
447  return StatusCode::SUCCESS;
448 }
449 //=============================================================================
450 
451 StatusCode FePGA::i2cWrite(){
452  debug("setting position of write i2c protocol","i2c write");
453  m_setupReg->read();
454  unsigned int data = m_setupReg->io()->dataU8()[0]; //WARNING !!!! What Values to put here ??
455  data &= ~(1 << 2) ;
456  m_setupReg->io()->setU8(0,data); //WARNING !!!! What Values to put here ??
457  m_setupReg->write();
458 
459  debug("setting subadd value in the frame","i2c write");
460  m_masterI2cReg->io()->defDataU8(3);
461  m_masterI2cReg->io()->setU8(0,m_i2cSubAdd&0xFF); //WARNING !!!! What Values to put here ??
462  m_masterI2cReg->io()->setU8(1,(m_i2cSubAdd>>8)&0xFF); //WARNING !!!! What Values to put here ??
463 
464  debug("setting buffer value in the frame","i2c write");
465  m_masterI2cReg->io()->setU8(2,m_i2cBuffer&0xFF); //WARNING !!!! What Values to put here ??
466 
467 
468  debug("i2c write","i2c write");
469  return m_masterI2cReg->write();
470 }
471 //====================================================================
472 unsigned long int FePGA::i2cRead(unsigned long int subadd){
473  setI2cSubAdd(subadd);
474  i2cRead();
475  return i2cData();
476 }
477 
478 //====================================================================
479 StatusCode FePGA::i2cWrite(unsigned long int subadd, unsigned long int value){
480  setI2cSubAdd(subadd);
481  setI2cBuffer(value);
482  return i2cWrite();
483 }
FePGA::setSpiSubAdd
StatusCode setSpiSubAdd(unsigned long int)
Definition: FePGA.cpp:228
RAM
Definition: RAM.h:16
FePGA::m_setupReg
Register * m_setupReg
Definition: FePGA.h:190
FePGA::setSpiAdd
StatusCode setSpiAdd(unsigned long int)
Definition: FePGA.cpp:77
FePGA::i2cData
unsigned long int i2cData()
Definition: FePGA.cpp:391
FePGA::MakeRAM
RAM * MakeRAM(std::string name, unsigned int add)
Definition: FePGA.cpp:65
RAM::setSize
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
FePGA::m_i2cBuffer
unsigned int m_i2cBuffer
Definition: FePGA.h:199
Attrib::add
void add(int attribut)
Definition: Attrib.h:67
IOobject::write
virtual StatusCode write()
Definition: IOobject.h:80
FePGA::i2cBuffer
unsigned long int i2cBuffer()
Definition: FePGA.cpp:384
IOdata::setU8
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
FePGA::m_addI2cReg
Register * m_addI2cReg
Definition: FePGA.h:202
Object::setName
void setName(std::string name)
Definition: Object.h:51
FePGA::setI2cSubAdd
StatusCode setI2cSubAdd(unsigned long int)
Definition: FePGA.cpp:412
IOobject::read
virtual StatusCode read()
Definition: IOobject.h:73
FePGA::m_rxSpiFifo
RAM * m_rxSpiFifo
Definition: FePGA.h:183
FePGA::i2cAdd
unsigned long int i2cAdd()
Definition: FePGA.cpp:404
Object::setType
void setType(std::string type)
Definition: Object.h:52
Object::setId
void setId(unsigned char id)
Definition: Object.h:53
FePGA::setI2cBuffer
StatusCode setI2cBuffer(unsigned long int)
Definition: FePGA.cpp:379
FePGA::m_txSpiFifo
RAM * m_txSpiFifo
Definition: FePGA.h:182
Object::debug
void debug(std::string mymsg)
Definition: Object.h:37
shell.data
def data(object, stream=None)
Definition: shell.py:150
IOdata::setAddress
StatusCode setAddress(U32 address)
Definition: IOdata.h:51
FePGA::i2cRead
StatusCode i2cRead()
Definition: FePGA.cpp:427
FePGA::MakeRegister
Register * MakeRegister(std::string name, unsigned int add)
Definition: FePGA.cpp:52
FePGA::setI2cAdd
StatusCode setI2cAdd(unsigned long int)
Definition: FePGA.cpp:398
FePGA::m_testFifo
RAM * m_testFifo
Definition: FePGA.h:185
FePGA::m_addSpiReg
Register * m_addSpiReg
Definition: FePGA.h:180
FePGA::m_masterI2cReg
Register * m_masterI2cReg
Definition: FePGA.h:201
FePGA::i2cGBTSCA
bool i2cGBTSCA()
Definition: FePGA.cpp:371
FePGA::spiRead
StatusCode spiRead(unsigned int, unsigned int, unsigned int *)
Definition: FePGA.cpp:102
FePGA::setI2cGBTSCA
StatusCode setI2cGBTSCA(bool)
Definition: FePGA.cpp:362
IOdata::dataU8
U8 * dataU8()
Definition: IOdata.h:214
FePGA::m_ctrlSpiReg
Register * m_ctrlSpiReg
Definition: FePGA.h:179
FePGA::spiSubAdd
unsigned long int spiSubAdd()
Definition: FePGA.cpp:232
Object::name
std::string name() const
Definition: Object.h:28
FePGA::i2cWrite
StatusCode i2cWrite()
Definition: FePGA.cpp:451
FePGA::spiGBTSCA
bool spiGBTSCA()
Definition: FePGA.cpp:220
FePGA::i2cSubAdd
unsigned long int i2cSubAdd()
Definition: FePGA.cpp:417
Hierarchy::addChild
virtual void addChild(Hierarchy *element)
Definition: Hierarchy.cpp:83
FePGA::spiWrite
StatusCode spiWrite(unsigned int, unsigned int, unsigned int *)
Definition: FePGA.cpp:84
IOdata::setWordSize
StatusCode setWordSize(IOdata::WordSize wordSize)
Definition: IOdata.h:126
IOdata::defDataU8
void defDataU8(unsigned long size)
Definition: IOdata.h:179
FePGA::m_spiSubAdd
unsigned int m_spiSubAdd
Definition: FePGA.h:194
FePGA::m_transmitSpiReg
Register * m_transmitSpiReg
Definition: FePGA.h:178
FePGA::m_usb
UsbFTMLInterface * m_usb
Definition: FePGA.h:173
FePGA::FePGA
FePGA()
Definition: FePGA.cpp:29
FePGA::setSpiGBTSCA
StatusCode setSpiGBTSCA(bool)
Definition: FePGA.cpp:211
FePGA::m_resetReg
Register * m_resetReg
Definition: FePGA.h:191
IOobject::io
IOdata * io()
Definition: IOobject.h:66
FePGA::m_i2cSubAdd
unsigned int m_i2cSubAdd
Definition: FePGA.h:198
Generated by   doxygen 1.8.13