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FePGA Class Reference

#include <FePGA.h>

Inheritance diagram for FePGA:
Element Hierarchy Object Attrib

Public Types

typedef unsigned long U32
 
typedef unsigned short U16
 
typedef unsigned char U8
 
- Public Types inherited from Attrib
enum  Attribut {
  UNDEFINED, PASSIVE, ACTIVE, INTERFACE,
  IO, IODATA, ELEMENT, HARDWARE,
  PROCESSUS, SOFTWARE
}
 

Public Member Functions

 FePGA ()
 
virtual ~FePGA ()
 
void help ()
 Destructor. More...
 
StatusCode init ()
 
void reset ()
 
void resetUsb ()
 
UsbFTMLInterfaceusb ()
 
UsbMLI2cBusi2c ()
 
UsbMLSpiBusspi ()
 
void update ()
 
RegistersetupReg ()
 
RegistermasterI2cReg ()
 
RegisteraddI2cReg ()
 
StatusCode testSequence ()
 
StatusCode setSpiGBTSCA (bool)
 
bool spiGBTSCA ()
 
StatusCode setSpiAdd (unsigned long int)
 
unsigned long int spiAdd ()
 
StatusCode setSpiSubAdd (unsigned long int)
 
unsigned long int spiSubAdd ()
 
StatusCode spiRead (unsigned int, unsigned int, unsigned int *)
 
StatusCode spiWrite (unsigned int, unsigned int, unsigned int *)
 
PyObject * spiRead (unsigned int, unsigned int)
 
StatusCode spiWrite (unsigned int, unsigned int, PyObject *)
 
unsigned int spiRead (unsigned int)
 
StatusCode spiWrite (unsigned int, unsigned int)
 
StatusCode setI2cGBTSCA (bool)
 
bool i2cGBTSCA ()
 
StatusCode setI2cBuffer (unsigned long int)
 
unsigned long int i2cBuffer ()
 
unsigned long int i2cData ()
 
StatusCode setI2cAdd (unsigned long int)
 
unsigned long int i2cAdd ()
 
StatusCode setI2cSubAdd (unsigned long int)
 
unsigned long int i2cSubAdd ()
 
StatusCode i2cRead ()
 
StatusCode i2cWrite ()
 
unsigned long int i2cRead (unsigned long int)
 
StatusCode i2cWrite (unsigned long int, unsigned long int)
 
StatusCode transmitSpi ()
 
- Public Member Functions inherited from Element
 Element ()
 Standard constructor. More...
 
virtual ~Element ()
 Destructor. More...
 
void recursiveInitElement ()
 
void recursiveInitCommunications ()
 
StatusCode setConnection (Hierarchy *)
 
Hierarchyconnection ()
 
- Public Member Functions inherited from Hierarchy
 Hierarchy ()
 Standard constructor. More...
 
virtual ~Hierarchy ()
 Destructor. More...
 
void clear ()
 
void setParent (Hierarchy *parent)
 
Hierarchyparent ()
 
Hierarchyparent (std::string)
 
Hierarchyorigin ()
 
virtual void addChild (Hierarchy *element)
 
std::vector< Hierarchy * > children ()
 
Hierarchychild (std::string)
 
HierarchychildTyped (std::string)
 
unsigned long numberOfChildren ()
 
bool hasChildren ()
 
void delChild (Hierarchy *)
 
void delChild (std::string)
 
std::string path (std::string=std::string(""))
 
std::string pathTyped (std::string=std::string(""))
 
void tree (std::string indent=std::string(""))
 
void tree ()
 
- Public Member Functions inherited from Object
 Object ()
 Standard constructor. More...
 
virtual ~Object ()
 Destructor. More...
 
std::string name () const
 
std::string type ()
 
unsigned char id ()
 
std::string title ()
 
void msgSvc (int level, std::string msg, std::string name)
 
void msg (std::string mymsg)
 
void verbose (std::string mymsg)
 
void debug (std::string mymsg)
 
void info (std::string mymsg)
 
void warning (std::string mymsg)
 
void error (std::string mymsg)
 
void fatal (std::string mymsg)
 
void msg (std::string mymsg, std::string name)
 
void verbose (std::string mymsg, std::string name)
 
void debug (std::string mymsg, std::string name)
 
void info (std::string mymsg, std::string name)
 
void warning (std::string mymsg, std::string name)
 
void error (std::string mymsg, std::string name)
 
void fatal (std::string mymsg, std::string name)
 
void setName (std::string name)
 
void setType (std::string type)
 
void setId (unsigned char id)
 
void setTitle (std::string title)
 
void setDllName (std::string dllName)
 
std::string dllName ()
 
- Public Member Functions inherited from Attrib
 Attrib ()
 Standard constructor. More...
 
virtual ~Attrib ()
 Destructor. More...
 
bool is (int attribut)
 
void add (int attribut)
 
void remove (int attribut)
 
std::string attributs ()
 

Private Member Functions

RegisterMakeRegister (std::string name, unsigned int add)
 
RAMMakeRAM (std::string name, unsigned int add)
 

Private Attributes

UsbFTMLInterfacem_usb
 
UsbMLI2cBusm_usbi2c
 
UsbMLSpiBusm_usbspi
 
Registerm_transmitSpiReg
 
Registerm_ctrlSpiReg
 
Registerm_addSpiReg
 
RAMm_txSpiFifo
 
RAMm_rxSpiFifo
 
RAMm_testFifo
 
Registerm_setupReg
 
Registerm_resetReg
 
Registerm_testSeqReg
 
unsigned int m_spiSubAdd
 
unsigned int m_i2cSubAdd
 
unsigned int m_i2cBuffer
 
Registerm_masterI2cReg
 
Registerm_addI2cReg
 

Additional Inherited Members

- Protected Attributes inherited from Element
Hierarchym_connection
 
- Protected Attributes inherited from Attrib
std::string m_attribString [10]
 

Detailed Description

Definition at line 23 of file FePGA.h.

Member Typedef Documentation

◆ U16

typedef unsigned short FePGA::U16

Definition at line 26 of file FePGA.h.

◆ U32

typedef unsigned long FePGA::U32

Definition at line 25 of file FePGA.h.

◆ U8

typedef unsigned char FePGA::U8

Definition at line 27 of file FePGA.h.

Constructor & Destructor Documentation

◆ FePGA()

FePGA::FePGA ( )

Definition at line 29 of file FePGA.cpp.

References Attrib::add(), Hierarchy::addChild(), Object::debug(), Attrib::ELEMENT, Attrib::HARDWARE, m_addSpiReg, m_ctrlSpiReg, m_resetReg, m_rxSpiFifo, m_setupReg, m_testFifo, m_transmitSpiReg, m_txSpiFifo, m_usb, MakeRAM(), MakeRegister(), Object::setId(), Object::setName(), and Object::setType().

29  : m_addSpiReg() {
30  setType("FePGA");
31  setId(0);
33  debug("FePGA built.","FePGA::FePGA");
34 
35  m_usb = new UsbFTMLInterface();
36  m_usb->setName("Usb");
37  addChild(m_usb);
38 
39  m_setupReg = MakeRegister("SetupReg", 0x01);
40  m_resetReg = MakeRegister("ResetReg", 0x02);
41  m_addSpiReg = MakeRegister("AddSpiReg", 0x03);
42  m_transmitSpiReg = MakeRegister("TransmitSpiReg", 0x0B);
43  m_ctrlSpiReg = MakeRegister("CtrlSpiReg", 0x0E);
44 
45  m_rxSpiFifo = MakeRAM("RxSpiFifo", 0x0C);
46  m_txSpiFifo = MakeRAM("TxSpiFifo", 0x0D);
47 
48  m_testFifo = MakeRAM("TestFifo", 0x05);
49 
50 }
Register * m_setupReg
Definition: FePGA.h:190
RAM * MakeRAM(std::string name, unsigned int add)
Definition: FePGA.cpp:65
void add(int attribut)
Definition: Attrib.h:67
void setName(std::string name)
Definition: Object.h:51
RAM * m_rxSpiFifo
Definition: FePGA.h:183
void setType(std::string type)
Definition: Object.h:52
void setId(unsigned char id)
Definition: Object.h:53
RAM * m_txSpiFifo
Definition: FePGA.h:182
void debug(std::string mymsg)
Definition: Object.h:37
Register * MakeRegister(std::string name, unsigned int add)
Definition: FePGA.cpp:52
RAM * m_testFifo
Definition: FePGA.h:185
Register * m_addSpiReg
Definition: FePGA.h:180
Register * m_ctrlSpiReg
Definition: FePGA.h:179
virtual void addChild(Hierarchy *element)
Definition: Hierarchy.cpp:83
Register * m_transmitSpiReg
Definition: FePGA.h:178
UsbFTMLInterface * m_usb
Definition: FePGA.h:173
Register * m_resetReg
Definition: FePGA.h:191

◆ ~FePGA()

virtual FePGA::~FePGA ( )
inlinevirtual

Definition at line 31 of file FePGA.h.

31 {};

Member Function Documentation

◆ addI2cReg()

Register* FePGA::addI2cReg ( )
inline

Definition at line 100 of file FePGA.h.

References m_addI2cReg.

100 { return m_addI2cReg; }
Register * m_addI2cReg
Definition: FePGA.h:202

◆ help()

void FePGA::help ( )
inlinevirtual

Destructor.

printout help for the element

Implements Element.

Definition at line 36 of file FePGA.h.

References Object::info(), and Object::name().

36 { info("FePGA "+name()+". No help.","FePGA::help"); };
void info(std::string mymsg)
Definition: Object.h:38
std::string name() const
Definition: Object.h:28

◆ i2c()

UsbMLI2cBus* FePGA::i2c ( )
inline

Definition at line 78 of file FePGA.h.

References m_usbi2c.

Referenced by BOOST_PYTHON_MODULE().

78  {
79  return m_usbi2c;
80  }
UsbMLI2cBus * m_usbi2c
Definition: FePGA.h:174

◆ i2cAdd()

unsigned long int FePGA::i2cAdd ( )

Definition at line 404 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_addI2cReg, and IOobject::read().

Referenced by testSequence().

404  {
405  m_addI2cReg->read();
406  return ( m_addI2cReg->io()->dataU8(0) + (m_addI2cReg->io()->dataU8(1)<<8) ) ; //WARNING !!!! What Values to put here ??
407 }
Register * m_addI2cReg
Definition: FePGA.h:202
virtual StatusCode read()
Definition: IOobject.h:73
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ i2cBuffer()

unsigned long int FePGA::i2cBuffer ( )

Definition at line 384 of file FePGA.cpp.

References m_i2cBuffer.

Referenced by testSequence().

384  {
385  return m_i2cBuffer;
386 }
unsigned int m_i2cBuffer
Definition: FePGA.h:199

◆ i2cData()

unsigned long int FePGA::i2cData ( )

Definition at line 391 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), and m_masterI2cReg.

Referenced by i2cRead(), and testSequence().

391  {
392  return ( ((m_masterI2cReg->io()->dataU8(0))&0xFF) ) ; //WARNING !!!! What Values to put here ??
393 }
Register * m_masterI2cReg
Definition: FePGA.h:201
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ i2cGBTSCA()

bool FePGA::i2cGBTSCA ( )

Definition at line 371 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_setupReg, and IOobject::read().

Referenced by testSequence().

371  {
372  m_setupReg->read();
373  return (! ( m_setupReg->io()->dataU8(0) & 1 ) ) ;
374 }
Register * m_setupReg
Definition: FePGA.h:190
virtual StatusCode read()
Definition: IOobject.h:73
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ i2cRead() [1/2]

StatusCode FePGA::i2cRead ( )

Definition at line 427 of file FePGA.cpp.

References shell::data(), IOdata::dataU8(), Object::debug(), IOdata::defDataU8(), IOobject::io(), m_i2cSubAdd, m_masterI2cReg, m_setupReg, IOobject::read(), IOdata::setU8(), StatusCode::SUCCESS, and IOobject::write().

Referenced by i2cRead(), and testSequence().

427  {
428  debug("setting position of read i2c protocol","i2c read");
429  m_setupReg->read();
430  unsigned int data = m_setupReg->io()->dataU8()[0];//WARNING !!!! What Values to put here ??
431  data |= (1 << 2) ;
432  m_setupReg->io()->setU8(0,data);
433  m_setupReg->write();
434 
435  debug("setting subadd value in the frame","i2c write");
436  m_masterI2cReg->io()->defDataU8(2);
437  m_masterI2cReg->io()->setU8(0,m_i2cSubAdd&0xFF);//WARNING !!!! What Values to put here ??
438  m_masterI2cReg->io()->setU8(1,(m_i2cSubAdd>>8)&0xFF);//WARNING !!!! What Values to put here ??
439 
440  debug("i2c write of the register","i2c read");
442 
443  debug("i2c read of the addressed register","i2c read");
444  m_masterI2cReg->io()->defDataU8(1);//WARNING !!!! What Values to put here ??
445  m_masterI2cReg->read();
446 
447  return StatusCode::SUCCESS;
448 }
Register * m_setupReg
Definition: FePGA.h:190
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
void debug(std::string mymsg)
Definition: Object.h:37
def data(object, stream=None)
Definition: shell.py:150
Register * m_masterI2cReg
Definition: FePGA.h:201
U8 * dataU8()
Definition: IOdata.h:214
void defDataU8(unsigned long size)
Definition: IOdata.h:179
IOdata * io()
Definition: IOobject.h:66
unsigned int m_i2cSubAdd
Definition: FePGA.h:198

◆ i2cRead() [2/2]

unsigned long int FePGA::i2cRead ( unsigned long int  subadd)

Definition at line 472 of file FePGA.cpp.

References i2cData(), i2cRead(), and setI2cSubAdd().

472  {
473  setI2cSubAdd(subadd);
474  i2cRead();
475  return i2cData();
476 }
unsigned long int i2cData()
Definition: FePGA.cpp:391
StatusCode setI2cSubAdd(unsigned long int)
Definition: FePGA.cpp:412
StatusCode i2cRead()
Definition: FePGA.cpp:427

◆ i2cSubAdd()

unsigned long int FePGA::i2cSubAdd ( )

Definition at line 417 of file FePGA.cpp.

References m_i2cSubAdd.

Referenced by testSequence().

417  {
418  return m_i2cSubAdd;
419 }
unsigned int m_i2cSubAdd
Definition: FePGA.h:198

◆ i2cWrite() [1/2]

StatusCode FePGA::i2cWrite ( )

Definition at line 451 of file FePGA.cpp.

References shell::data(), IOdata::dataU8(), Object::debug(), IOdata::defDataU8(), IOobject::io(), m_i2cBuffer, m_i2cSubAdd, m_masterI2cReg, m_setupReg, IOobject::read(), IOdata::setU8(), and IOobject::write().

Referenced by i2cWrite(), and testSequence().

451  {
452  debug("setting position of write i2c protocol","i2c write");
453  m_setupReg->read();
454  unsigned int data = m_setupReg->io()->dataU8()[0]; //WARNING !!!! What Values to put here ??
455  data &= ~(1 << 2) ;
456  m_setupReg->io()->setU8(0,data); //WARNING !!!! What Values to put here ??
457  m_setupReg->write();
458 
459  debug("setting subadd value in the frame","i2c write");
460  m_masterI2cReg->io()->defDataU8(3);
461  m_masterI2cReg->io()->setU8(0,m_i2cSubAdd&0xFF); //WARNING !!!! What Values to put here ??
462  m_masterI2cReg->io()->setU8(1,(m_i2cSubAdd>>8)&0xFF); //WARNING !!!! What Values to put here ??
463 
464  debug("setting buffer value in the frame","i2c write");
465  m_masterI2cReg->io()->setU8(2,m_i2cBuffer&0xFF); //WARNING !!!! What Values to put here ??
466 
467 
468  debug("i2c write","i2c write");
469  return m_masterI2cReg->write();
470 }
Register * m_setupReg
Definition: FePGA.h:190
unsigned int m_i2cBuffer
Definition: FePGA.h:199
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
void debug(std::string mymsg)
Definition: Object.h:37
def data(object, stream=None)
Definition: shell.py:150
Register * m_masterI2cReg
Definition: FePGA.h:201
U8 * dataU8()
Definition: IOdata.h:214
void defDataU8(unsigned long size)
Definition: IOdata.h:179
IOdata * io()
Definition: IOobject.h:66
unsigned int m_i2cSubAdd
Definition: FePGA.h:198

◆ i2cWrite() [2/2]

StatusCode FePGA::i2cWrite ( unsigned long int  subadd,
unsigned long int  value 
)

Definition at line 479 of file FePGA.cpp.

References i2cWrite(), setI2cBuffer(), and setI2cSubAdd().

479  {
480  setI2cSubAdd(subadd);
481  setI2cBuffer(value);
482  return i2cWrite();
483 }
StatusCode setI2cSubAdd(unsigned long int)
Definition: FePGA.cpp:412
StatusCode setI2cBuffer(unsigned long int)
Definition: FePGA.cpp:379
StatusCode i2cWrite()
Definition: FePGA.cpp:451

◆ init()

StatusCode FePGA::init ( )
inlinevirtual

init the component

Returns
void

Implements Element.

Definition at line 42 of file FePGA.h.

References StatusCode::SUCCESS.

42  {
43  return StatusCode::SUCCESS;
44  };

◆ MakeRAM()

RAM * FePGA::MakeRAM ( std::string  name,
unsigned int  add 
)
private

Definition at line 65 of file FePGA.cpp.

References Hierarchy::addChild(), IOobject::io(), m_usb, IOdata::setAddress(), Object::setName(), and RAM::setSize().

Referenced by FePGA(), and transmitSpi().

65  {
66 
67  RAM* ram = new RAM();
68  ram ->setName(name);
69  ram ->setSize(16, 1024);
70  ram ->io()->setAddress(add);
71  m_usb ->addChild(ram);
72 
73  return ram;
74 
75 }
Definition: RAM.h:16
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
void add(int attribut)
Definition: Attrib.h:67
void setName(std::string name)
Definition: Object.h:51
StatusCode setAddress(U32 address)
Definition: IOdata.h:51
std::string name() const
Definition: Object.h:28
virtual void addChild(Hierarchy *element)
Definition: Hierarchy.cpp:83
UsbFTMLInterface * m_usb
Definition: FePGA.h:173
IOdata * io()
Definition: IOobject.h:66

◆ MakeRegister()

Register * FePGA::MakeRegister ( std::string  name,
unsigned int  add 
)
private

Definition at line 52 of file FePGA.cpp.

References Hierarchy::addChild(), IOdata::Byte, IOdata::defDataU8(), IOobject::io(), m_usb, IOdata::setAddress(), Object::setName(), and IOdata::setWordSize().

Referenced by FePGA(), and transmitSpi().

52  {
53 
54  Register* reg = new Register();
55  reg ->setName(name);
56  reg ->io()->defDataU8(2);
57  reg ->io()->setAddress(add);
58  reg ->io()->setWordSize(IOdata::Byte);
59  m_usb ->addChild(reg);
60 
61  return reg;
62 
63 }
void add(int attribut)
Definition: Attrib.h:67
void setName(std::string name)
Definition: Object.h:51
StatusCode setAddress(U32 address)
Definition: IOdata.h:51
std::string name() const
Definition: Object.h:28
virtual void addChild(Hierarchy *element)
Definition: Hierarchy.cpp:83
StatusCode setWordSize(IOdata::WordSize wordSize)
Definition: IOdata.h:126
void defDataU8(unsigned long size)
Definition: IOdata.h:179
UsbFTMLInterface * m_usb
Definition: FePGA.h:173
IOdata * io()
Definition: IOobject.h:66

◆ masterI2cReg()

Register* FePGA::masterI2cReg ( )
inline

Definition at line 99 of file FePGA.h.

References m_masterI2cReg.

99 { return m_masterI2cReg; }
Register * m_masterI2cReg
Definition: FePGA.h:201

◆ reset()

void FePGA::reset ( )
inlinevirtual

Resets the Element so that is is in a standard and safe situation. Different from Element::init which configure the Element. Element::reset() is more an Emergency pull. It is often/usually called by the recursiveInitElement method at the start of the program.

Implements Element.

Definition at line 54 of file FePGA.h.

References Object::info(), IOobject::io(), m_resetReg, IOdata::setU8(), and IOobject::write().

Referenced by CU_v1::reset().

54  {
55  info("FePGA reset.");
56  m_resetReg->io()->setU8(0,1);
57  m_resetReg->io()->setU8(1,0);
58  m_resetReg->write();
59  };
void info(std::string mymsg)
Definition: Object.h:38
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
Register * m_resetReg
Definition: FePGA.h:191
IOdata * io()
Definition: IOobject.h:66

◆ resetUsb()

void FePGA::resetUsb ( )
inline

Definition at line 63 of file FePGA.h.

References IOobject::dump(), Object::info(), IOobject::io(), m_resetReg, IOdata::setU8(), and IOobject::write().

63  {
64  info("Usb TxRx reset.");
65  m_resetReg->io()->setU8(0,2);
66  m_resetReg->io()->setU8(1,0);
67  m_resetReg->dump();
68  m_resetReg->write();
69 
70  };
void info(std::string mymsg)
Definition: Object.h:38
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
void dump()
Definition: IOobject.h:92
Register * m_resetReg
Definition: FePGA.h:191
IOdata * io()
Definition: IOobject.h:66

◆ setI2cAdd()

StatusCode FePGA::setI2cAdd ( unsigned long int  value)

Definition at line 398 of file FePGA.cpp.

References IOobject::io(), m_addI2cReg, IOdata::setU8(), and IOobject::write().

Referenced by testSequence().

398  {
399  m_addI2cReg->io()->setU8(0,value&0xFF); //WARNING !!!! What Values to put here ??
400  m_addI2cReg->io()->setU8(1,(value&0xFF00)>>8); //WARNING !!!! What Values to put here ??
401  return m_addI2cReg->write();
402 }
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
Register * m_addI2cReg
Definition: FePGA.h:202
IOdata * io()
Definition: IOobject.h:66

◆ setI2cBuffer()

StatusCode FePGA::setI2cBuffer ( unsigned long int  value)

Definition at line 379 of file FePGA.cpp.

References m_i2cBuffer, and StatusCode::SUCCESS.

Referenced by i2cWrite(), and testSequence().

379  {
380  m_i2cBuffer = value;
381  return StatusCode::SUCCESS;
382 }
unsigned int m_i2cBuffer
Definition: FePGA.h:199

◆ setI2cGBTSCA()

StatusCode FePGA::setI2cGBTSCA ( bool  value)

Definition at line 362 of file FePGA.cpp.

References shell::data(), IOdata::dataU8(), IOobject::io(), m_setupReg, IOobject::read(), IOdata::setU8(), and IOobject::write().

Referenced by testSequence().

362  {
363  m_setupReg->read();
364  unsigned int data=m_setupReg->io()->dataU8()[0];
365  if (!value) data |= 1 ;
366  else data &= ~1 ;
367  m_setupReg->io()->setU8(0,data);
368  return m_setupReg->write();
369 }
Register * m_setupReg
Definition: FePGA.h:190
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
def data(object, stream=None)
Definition: shell.py:150
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ setI2cSubAdd()

StatusCode FePGA::setI2cSubAdd ( unsigned long int  value)

Definition at line 412 of file FePGA.cpp.

References m_i2cSubAdd, and StatusCode::SUCCESS.

Referenced by i2cRead(), i2cWrite(), and testSequence().

412  {
413  m_i2cSubAdd = value;
414  return StatusCode::SUCCESS;
415 }
unsigned int m_i2cSubAdd
Definition: FePGA.h:198

◆ setSpiAdd()

StatusCode FePGA::setSpiAdd ( unsigned long int  value)

Definition at line 77 of file FePGA.cpp.

References IOobject::io(), m_addSpiReg, IOdata::setU8(), and IOobject::write().

Referenced by BOOST_PYTHON_MODULE(), and testSequence().

77  {
78  m_addSpiReg->io()->setU8(0,value&0xFF);
79  m_addSpiReg->io()->setU8(1,(value>>8) & 0xFF);
80  return m_addSpiReg->write();
81 }
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
Register * m_addSpiReg
Definition: FePGA.h:180
IOdata * io()
Definition: IOobject.h:66

◆ setSpiGBTSCA()

StatusCode FePGA::setSpiGBTSCA ( bool  value)

Definition at line 211 of file FePGA.cpp.

References shell::data(), IOdata::dataU8(), IOobject::io(), m_setupReg, IOobject::read(), IOdata::setU8(), and IOobject::write().

Referenced by BOOST_PYTHON_MODULE(), and testSequence().

211  {
212  m_setupReg->read();
213  unsigned int data=m_setupReg->io()->dataU8()[0];
214  if (!value) data |= 2 ;
215  else data &= ~2 ;
216  m_setupReg->io()->setU8(0,data);
217  return m_setupReg->write();
218 }
Register * m_setupReg
Definition: FePGA.h:190
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
def data(object, stream=None)
Definition: shell.py:150
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ setSpiSubAdd()

StatusCode FePGA::setSpiSubAdd ( unsigned long int  value)

Definition at line 228 of file FePGA.cpp.

References m_spiSubAdd.

Referenced by testSequence().

228  {
229  m_spiSubAdd = value & 0x7F; //WARNING !!!! What Values to put here ??
230 }
unsigned int m_spiSubAdd
Definition: FePGA.h:194

◆ setupReg()

Register* FePGA::setupReg ( )
inline

Definition at line 97 of file FePGA.h.

References m_setupReg.

Referenced by BOOST_PYTHON_MODULE().

97 { return m_setupReg; }
Register * m_setupReg
Definition: FePGA.h:190

◆ spi()

UsbMLSpiBus* FePGA::spi ( )
inline

Definition at line 82 of file FePGA.h.

References m_usbspi.

Referenced by BOOST_PYTHON_MODULE().

82  {
83  return m_usbspi;
84  }
UsbMLSpiBus * m_usbspi
Definition: FePGA.h:175

◆ spiAdd()

unsigned long int FePGA::spiAdd ( )

Referenced by testSequence().

◆ spiGBTSCA()

bool FePGA::spiGBTSCA ( )

Definition at line 220 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_setupReg, and IOobject::read().

Referenced by testSequence().

220  {
221  m_setupReg->read();
222  return (! ( m_setupReg->io()->dataU8(0) & 2 ) ) ;
223 }
Register * m_setupReg
Definition: FePGA.h:190
virtual StatusCode read()
Definition: IOobject.h:73
U8 * dataU8()
Definition: IOdata.h:214
IOdata * io()
Definition: IOobject.h:66

◆ spiRead() [1/3]

StatusCode FePGA::spiRead ( unsigned int  subadd,
unsigned int  nwords,
unsigned int *  values 
)

Definition at line 102 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_ctrlSpiReg, m_rxSpiFifo, m_transmitSpiReg, m_txSpiFifo, IOobject::read(), RAM::setSize(), IOdata::setU8(), and IOobject::write().

Referenced by BOOST_PYTHON_MODULE(), CU_v1::readFifo(), and testSequence().

102  {
103  // mode block pour read les mots dans un vecteur values
104 
105  unsigned int val = subadd | 0x80 ;
106  m_txSpiFifo->setSize(16,1);
107  m_rxSpiFifo->setSize(16,nwords+1);
108  m_ctrlSpiReg->io()->setU8(0,(nwords+1)&0xFF);
109  m_ctrlSpiReg->io()->setU8(1,((nwords+1)>>8)&0xFF);
110  m_ctrlSpiReg->write();
111  m_txSpiFifo->io()->setU8(0,val);
112  m_txSpiFifo->io()->setU8(1,0);
113  m_txSpiFifo->write();
114  StatusCode status = m_transmitSpiReg->write();
115  // usleep(100000);
116  m_rxSpiFifo->read();
117  for (int w=0; w<nwords; ++w) {
118  values[w]=((m_rxSpiFifo->io()->dataU8(2*w+2))&0xFF)+
119  (((m_rxSpiFifo->io()->dataU8(2*w+3))&0xFF)<<8);
120  }
121  return status;
122 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
RAM * m_rxSpiFifo
Definition: FePGA.h:183
RAM * m_txSpiFifo
Definition: FePGA.h:182
U8 * dataU8()
Definition: IOdata.h:214
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ spiRead() [2/3]

PyObject * FePGA::spiRead ( unsigned int  subadd,
unsigned int  nwords 
)

Definition at line 144 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_ctrlSpiReg, m_rxSpiFifo, m_transmitSpiReg, m_txSpiFifo, IOobject::read(), RAM::setSize(), IOdata::setU8(), and IOobject::write().

144  {
145  unsigned int val = subadd | 0x80 ;
146  m_txSpiFifo->setSize(16,1);
147  m_rxSpiFifo->setSize(16,nwords+1);
148  m_ctrlSpiReg->io()->setU8(0,(nwords+1)&0xFF);
149  m_ctrlSpiReg->io()->setU8(1,((nwords+1)>>8)&0xFF);
150  m_ctrlSpiReg->write();
151  // m_ctrlSpiReg->read();
152  // m_ctrlSpiReg->dump();
153  m_txSpiFifo->io()->setU8(0,val);
154  m_txSpiFifo->io()->setU8(1,0);
155  m_txSpiFifo->write();
156  StatusCode status = m_transmitSpiReg->write();
157  // usleep(100000);
158  m_rxSpiFifo->read();
159  PyObject* values = PyList_New(0);
160  for (int w=0; w<nwords; ++w) {
161  // m_rxSpiFifo->dump();
162  PyList_Append(values,
163  PyInt_FromLong( (long int) (
164  ((m_rxSpiFifo->io()->dataU8(2*w+2))&0xFF) +
165  (((m_rxSpiFifo->io()->dataU8(2*w+3))&0xFF)<<8)
166  )));
167  }
168  return values;
169 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
RAM * m_rxSpiFifo
Definition: FePGA.h:183
RAM * m_txSpiFifo
Definition: FePGA.h:182
U8 * dataU8()
Definition: IOdata.h:214
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ spiRead() [3/3]

unsigned int FePGA::spiRead ( unsigned int  subadd)

Definition at line 187 of file FePGA.cpp.

References IOdata::dataU8(), IOobject::io(), m_ctrlSpiReg, m_rxSpiFifo, m_transmitSpiReg, m_txSpiFifo, IOobject::read(), RAM::setSize(), IOdata::setU8(), and IOobject::write().

187  {
188  unsigned int val = subadd | 0x80 ;
189  m_txSpiFifo->setSize(16,1);
190  m_rxSpiFifo->setSize(16,1);
191  m_ctrlSpiReg->io()->setU8(0,1);
192  m_ctrlSpiReg->io()->setU8(1,0);
193  m_ctrlSpiReg->write();
194  m_txSpiFifo->io()->setU8(0,val);
195  m_txSpiFifo->io()->setU8(1,0);
196  m_txSpiFifo->write();
197  // m_txSpiFifo->dump();
198  StatusCode status = m_transmitSpiReg->write();
199  // usleep(100000);
200  m_rxSpiFifo->read();
201  // m_rxSpiFifo->dump();
202  return ((m_rxSpiFifo->io()->dataU8(0))&0xFF) + (((m_rxSpiFifo->io()->dataU8(1))&0xFF)<<8);
203 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
virtual StatusCode read()
Definition: IOobject.h:73
RAM * m_rxSpiFifo
Definition: FePGA.h:183
RAM * m_txSpiFifo
Definition: FePGA.h:182
U8 * dataU8()
Definition: IOdata.h:214
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ spiSubAdd()

unsigned long int FePGA::spiSubAdd ( )

Definition at line 232 of file FePGA.cpp.

References m_spiSubAdd.

Referenced by testSequence().

232  {
233  return ( m_spiSubAdd ) ;
234 }
unsigned int m_spiSubAdd
Definition: FePGA.h:194

◆ spiWrite() [1/3]

StatusCode FePGA::spiWrite ( unsigned int  subadd,
unsigned int  nwords,
unsigned int *  values 
)

Definition at line 84 of file FePGA.cpp.

References IOobject::io(), m_ctrlSpiReg, m_transmitSpiReg, m_txSpiFifo, RAM::setSize(), IOdata::setU8(), and IOobject::write().

Referenced by BOOST_PYTHON_MODULE(), and testSequence().

84  {
85  // mode block pour write les mots dans un vecteur values
86 
87  unsigned int val = subadd & 0x7F;
88  m_txSpiFifo->setSize(16,nwords+1);
89  m_ctrlSpiReg->io()->setU8(0,nwords&0xFF);
90  m_ctrlSpiReg->io()->setU8(1,(nwords>>8)&0xFF);
92  m_txSpiFifo->io()->setU8(0,val);
93  m_txSpiFifo->io()->setU8(1,0);
94  for (int w=0; w<nwords; ++w) {
95  m_txSpiFifo->io()->setU8(2*w+2,values[w]&0xFF);
96  m_txSpiFifo->io()->setU8(2*w+3,(values[w]>>8)&0xFF);
97  }
98  m_txSpiFifo->write();
99  return m_transmitSpiReg->write();
100 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
RAM * m_txSpiFifo
Definition: FePGA.h:182
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ spiWrite() [2/3]

StatusCode FePGA::spiWrite ( unsigned int  subadd,
unsigned int  nwords,
PyObject *  value 
)

Definition at line 124 of file FePGA.cpp.

References IOobject::io(), m_ctrlSpiReg, m_transmitSpiReg, m_txSpiFifo, RAM::setSize(), IOdata::setU8(), and IOobject::write().

124  {
125  unsigned int val = subadd & 0x7F;
126  m_txSpiFifo->setSize(16,nwords+1);
127  m_ctrlSpiReg->io()->setU8(0,nwords&0xFF);
128  m_ctrlSpiReg->io()->setU8(1,(nwords>>8)&0xFF);
129  m_ctrlSpiReg->write();
130  // m_ctrlSpiReg->read();
131  // m_ctrlSpiReg->dump();
132  m_txSpiFifo->io()->setU8(0,val);
133  m_txSpiFifo->io()->setU8(1,0);
134  for (int w=0; w<nwords; ++w) {
135  val = PyInt_AsLong(PyList_GetItem(value,w));
136  m_txSpiFifo->io()->setU8(2*w+2,val&0xFF);
137  m_txSpiFifo->io()->setU8(2*w+3,(val>>8)&0xFF);
138  }
139  // m_txSpiFifo->dump();
140  m_txSpiFifo->write();
141  return m_transmitSpiReg->write();
142 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
RAM * m_txSpiFifo
Definition: FePGA.h:182
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ spiWrite() [3/3]

StatusCode FePGA::spiWrite ( unsigned int  subadd,
unsigned int  value 
)

Definition at line 171 of file FePGA.cpp.

References IOobject::io(), m_ctrlSpiReg, m_transmitSpiReg, m_txSpiFifo, RAM::setSize(), IOdata::setU8(), and IOobject::write().

171  {
172  unsigned int val = subadd & 0x7F;
173  m_txSpiFifo->setSize(16,2);
174  m_ctrlSpiReg->io()->setU8(0,1);
175  m_ctrlSpiReg->io()->setU8(1,0);
176  m_ctrlSpiReg->write();
177  // m_ctrlSpiReg->read();
178  m_txSpiFifo->io()->setU8(0,val);
179  m_txSpiFifo->io()->setU8(1,0);
180  m_txSpiFifo->io()->setU8(2,value&0xFF);
181  m_txSpiFifo->io()->setU8(3,(value>>8)&0xFF);
182  m_txSpiFifo->write();
183  // m_txSpiFifo->dump();
184  return m_transmitSpiReg->write();
185 }
StatusCode setSize(unsigned int, unsigned int)
Definition: RAM.cpp:29
virtual StatusCode write()
Definition: IOobject.h:80
StatusCode setU8(unsigned long int, U8)
Definition: IOdata.cpp:43
RAM * m_txSpiFifo
Definition: FePGA.h:182
Register * m_ctrlSpiReg
Definition: FePGA.h:179
Register * m_transmitSpiReg
Definition: FePGA.h:178
IOdata * io()
Definition: IOobject.h:66

◆ testSequence()

StatusCode FePGA::testSequence ( )
inline

Definition at line 102 of file FePGA.h.

References i2cAdd(), i2cBuffer(), i2cData(), i2cGBTSCA(), i2cRead(), i2cSubAdd(), i2cWrite(), Object::info(), m_testSeqReg, setI2cAdd(), setI2cBuffer(), setI2cGBTSCA(), setI2cSubAdd(), setSpiAdd(), setSpiGBTSCA(), setSpiSubAdd(), spiAdd(), spiGBTSCA(), spiRead(), spiSubAdd(), spiWrite(), and IOobject::write().

102  {
103  info("FePGA testSequence.");
104  return m_testSeqReg->write();
105  };
void info(std::string mymsg)
Definition: Object.h:38
virtual StatusCode write()
Definition: IOobject.h:80
Register * m_testSeqReg
Definition: FePGA.h:192

◆ transmitSpi()

StatusCode FePGA::transmitSpi ( )
inline

Definition at line 163 of file FePGA.h.

References Attrib::add(), m_transmitSpiReg, MakeRAM(), MakeRegister(), Object::name(), and IOobject::write().

163  {
164  return m_transmitSpiReg->write();
165  }
virtual StatusCode write()
Definition: IOobject.h:80
Register * m_transmitSpiReg
Definition: FePGA.h:178

◆ update()

void FePGA::update ( )
inlinevirtual

◆ usb()

UsbFTMLInterface* FePGA::usb ( )
inline

Definition at line 74 of file FePGA.h.

References m_usb.

Referenced by BOOST_PYTHON_MODULE().

74  {
75  return m_usb;
76  }
UsbFTMLInterface * m_usb
Definition: FePGA.h:173

Member Data Documentation

◆ m_addI2cReg

Register* FePGA::m_addI2cReg
private

Definition at line 202 of file FePGA.h.

Referenced by addI2cReg(), i2cAdd(), and setI2cAdd().

◆ m_addSpiReg

Register* FePGA::m_addSpiReg
private

Definition at line 180 of file FePGA.h.

Referenced by FePGA(), and setSpiAdd().

◆ m_ctrlSpiReg

Register* FePGA::m_ctrlSpiReg
private

Definition at line 179 of file FePGA.h.

Referenced by FePGA(), spiRead(), and spiWrite().

◆ m_i2cBuffer

unsigned int FePGA::m_i2cBuffer
private

Definition at line 199 of file FePGA.h.

Referenced by i2cBuffer(), i2cWrite(), and setI2cBuffer().

◆ m_i2cSubAdd

unsigned int FePGA::m_i2cSubAdd
private

Definition at line 198 of file FePGA.h.

Referenced by i2cRead(), i2cSubAdd(), i2cWrite(), and setI2cSubAdd().

◆ m_masterI2cReg

Register* FePGA::m_masterI2cReg
private

Definition at line 201 of file FePGA.h.

Referenced by i2cData(), i2cRead(), i2cWrite(), and masterI2cReg().

◆ m_resetReg

Register* FePGA::m_resetReg
private

Definition at line 191 of file FePGA.h.

Referenced by FePGA(), reset(), and resetUsb().

◆ m_rxSpiFifo

RAM* FePGA::m_rxSpiFifo
private

Definition at line 183 of file FePGA.h.

Referenced by FePGA(), and spiRead().

◆ m_setupReg

Register* FePGA::m_setupReg
private

Definition at line 190 of file FePGA.h.

Referenced by FePGA(), i2cGBTSCA(), i2cRead(), i2cWrite(), setI2cGBTSCA(), setSpiGBTSCA(), setupReg(), and spiGBTSCA().

◆ m_spiSubAdd

unsigned int FePGA::m_spiSubAdd
private

Definition at line 194 of file FePGA.h.

Referenced by setSpiSubAdd(), and spiSubAdd().

◆ m_testFifo

RAM* FePGA::m_testFifo
private

Definition at line 185 of file FePGA.h.

Referenced by FePGA().

◆ m_testSeqReg

Register* FePGA::m_testSeqReg
private

Definition at line 192 of file FePGA.h.

Referenced by testSequence().

◆ m_transmitSpiReg

Register* FePGA::m_transmitSpiReg
private

Definition at line 178 of file FePGA.h.

Referenced by FePGA(), spiRead(), spiWrite(), and transmitSpi().

◆ m_txSpiFifo

RAM* FePGA::m_txSpiFifo
private

Definition at line 182 of file FePGA.h.

Referenced by FePGA(), spiRead(), and spiWrite().

◆ m_usb

UsbFTMLInterface* FePGA::m_usb
private

Definition at line 173 of file FePGA.h.

Referenced by FePGA(), MakeRAM(), MakeRegister(), and usb().

◆ m_usbi2c

UsbMLI2cBus* FePGA::m_usbi2c
private

Definition at line 174 of file FePGA.h.

Referenced by i2c().

◆ m_usbspi

UsbMLSpiBus* FePGA::m_usbspi
private

Definition at line 175 of file FePGA.h.

Referenced by spi().


The documentation for this class was generated from the following files: