Python.cpp

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#include <vector>
#include <list>

#include "Processus.h"

#include "Element.h"
#include "FEB_v1.h"
#include "CU_v1.h"
#include "SeqPGA.h"
#include "FePGA.h"
#include "UsbFTMLInterface.h"
#include "UsbMLSpiBus.h"
#include "UsbMLI2cBus.h"
#include "ICPhaser.h"

#include "TestUSB.h"
#include "TestSPI.h"
#include "TestI2C.h"
#include "Acquisition.h"

#include <boost/python.hpp>
#include <boost/python/suite/indexing/vector_indexing_suite.hpp>

using namespace boost::python;

BOOST_PYTHON_MODULE(libCatCaloUpgrade)
{


  StatusCode (FEB_v1::*setOutputEport1)(int, int, int, int) = (&FEB_v1::setOutputEport);
  StatusCode (FEB_v1::*setOutputEport2)(int, int, int) = (&FEB_v1::setOutputEport);

  int (FEB_v1::*latencyEport1)(int, int) = (&FEB_v1::latencyEport);
  int (FEB_v1::*latencyEport2)(int) = (&FEB_v1::latencyEport);

  int (FEB_v1::*clockPhaseEport1)(int, int) = (&FEB_v1::clockPhaseEport);
  int (FEB_v1::*clockPhaseEport2)(int) = (&FEB_v1::clockPhaseEport);

  class_<FEB_v1, bases <Element> >("FEB_v1")
    .def("seqPga"           ,&FEB_v1::seqPga,return_value_policy<reference_existing_object>())
    .def("ramInj"           ,&FEB_v1::ramInj,return_value_policy<reference_existing_object>())
    .def("ramSpy"           ,&FEB_v1::ramSpy,return_value_policy<reference_existing_object>())
   
    .def("testSequence"     ,&FEB_v1::testSequence)
    .def("setExtTrig"       ,&FEB_v1::setExtTrig)
    .def("extTrig"          ,&FEB_v1::extTrig)

    .def("readFifoSpyFE"    ,&FEB_v1::readFifoSpyFE)
    .def("readFifoLLTFE"    ,&FEB_v1::readFifoLLTFE)
    .def("readFifoLLT"      ,&FEB_v1::readFifoLLT)
    .def("readFifoInjectFE" ,&FEB_v1::readFifoInjectFE)
    .def("writeFifoSpyFE"   ,&FEB_v1::writeFifoSpyFE)
    .def("writeFifoLLTFE"   ,&FEB_v1::writeFifoLLTFE)
    .def("writeFifoLLT"     ,&FEB_v1::writeFifoLLT)
    .def("writeFifoInjectFE",&FEB_v1::writeFifoInjectFE)
    .def("writeDataFifoInjectFE",&FEB_v1::writeDataFifoInjectFE)

    .def("latencyLLT"       ,&FEB_v1::latencyLLT)
    .def("setLatencyLLT"       ,&FEB_v1::setLatencyLLT)
    .def("setLatencyLLTCorner" ,&FEB_v1::setLatencyLLTCorner)
    .def("setLatencyLLTUpNb"   ,&FEB_v1::setLatencyLLTUpNb)
    .def("setLatencyLLTSideNb" ,&FEB_v1::setLatencyLLTSideNb)

    .def("maskLLT"      ,&FEB_v1::maskLLT)
    .def("setMaskLLT"       ,&FEB_v1::setMaskLLT)
    .def("setMaskLLTCorner" ,&FEB_v1::setMaskLLTCorner)
    .def("setMaskLLTUpNb"   ,&FEB_v1::setMaskLLTUpNb)
    .def("setMaskLLTSideNb" ,&FEB_v1::setMaskLLTSideNb)


    .def("resetFifoSpyFE"    ,&FEB_v1::resetFifoSpyFE)
    .def("resetFifoInjectFE" ,&FEB_v1::resetFifoInjectFE)
    .def("resetSpi"          ,&FEB_v1::resetSpi)
    .def("resetFE"           ,&FEB_v1::resetFE)
    
    .def("setSpareForTrigEnable"   ,&FEB_v1::setSpareForTrigEnable)
    .def("spareForTrigEnable"      ,&FEB_v1::spareForTrigEnable)
    .def("setProbeEnable"   ,&FEB_v1::setProbeEnable)
    .def("probeEnable"      ,&FEB_v1::probeEnable)
    .def("setTestDuration"  ,&FEB_v1::setTestDuration)
    .def("testDuration"     ,&FEB_v1::testDuration)
    .def("setStopInjLoop" ,&FEB_v1::setStopInjLoop)
    .def("stopInjLoop"    ,&FEB_v1::stopInjLoop)
    .def("setSpyModeSeq"    ,&FEB_v1::setSpyModeSeq)
    .def("spyModeSeq"       ,&FEB_v1::spyModeSeq)
    .def("setSpyModeFE"     ,&FEB_v1::setSpyModeFE)
    .def("spyModeFE"        ,&FEB_v1::spyModeFE)
    .def("setSpyModeFE"     ,&FEB_v1::setSpyModeFE)
    .def("spyModeFE"        ,&FEB_v1::spyModeFE)
    .def("setDisableSubtract",&FEB_v1::setDisableSubtract)
    .def("disableSubtract"   ,&FEB_v1::disableSubtract)
    .def("setOldSubtract"   ,&FEB_v1::setOldSubtract)
    .def("oldSubtract"      ,&FEB_v1::oldSubtract)
    .def("setThreshold"     ,&FEB_v1::setThreshold)
    .def("threshold"        ,&FEB_v1::threshold)
    .def("setLatency"       ,&FEB_v1::setLatency)
    .def("latency"          ,&FEB_v1::latency)
    .def("setSpyModeFE"     ,&FEB_v1::setSpyModeFE)
    .def("spyModeFE"        ,&FEB_v1::spyModeFE)
    .def("setSpyModeFE"     ,&FEB_v1::setSpyModeFE)
    .def("spyModeFE"        ,&FEB_v1::spyModeFE)
    .def("setInjectModeFE"  ,&FEB_v1::setInjectModeFE)
    .def("injectModeFE"     ,&FEB_v1::injectModeFE)
    .def("statusRegister"   ,&FEB_v1::statusRegister)
    .def("setEnableBXIDReset" ,&FEB_v1::setEnableBXIDReset)
    .def("enableBXIDReset"    ,&FEB_v1::enableBXIDReset)

    .def("setGain4"                  ,&FEB_v1::setGain4)
    .def("setPseudoADCEnable"        ,&FEB_v1::setPseudoADCEnable)
    .def("setPseudoPMEnable"         ,&FEB_v1::setPseudoPMEnable)
    .def("setGlobalPseudoPMEnable"   ,&FEB_v1::setGlobalPseudoPMEnable)
    .def("setClockFallingEdge" ,&FEB_v1::setClockFallingEdge)
    .def("setCalibCte"         ,&FEB_v1::setCalibCte)
    .def("gain4"               ,&FEB_v1::gain4)
    .def("pseudoADCEnable"     ,&FEB_v1::pseudoADCEnable)
    .def("pseudoPMEnable"      ,&FEB_v1::pseudoPMEnable)
    .def("globalPseudoPMEnable",&FEB_v1::globalPseudoPMEnable)
    .def("setClockFallingEdge" ,&FEB_v1::setClockFallingEdge)
    .def("clockFallingEdge"    ,&FEB_v1::clockFallingEdge)
    .def("setClock80MHzFallingEdge" ,&FEB_v1::setClock80MHzFallingEdge)
    .def("clock80MHzFallingEdge"    ,&FEB_v1::clock80MHzFallingEdge)
    .def("setCalibCte"         ,&FEB_v1::setCalibCte)
    .def("calibCte"            ,&FEB_v1::calibCte)
    
    .def("setGbtMode"          ,&FEB_v1::setGbtMode)
    .def("gbtMode"             ,&FEB_v1::gbtMode)
    .def("setGbtDataPath"      ,&FEB_v1::setGbtDataPath)
    .def("gbtDataPath"         ,&FEB_v1::gbtDataPath)
    .def("setGbtTrackMode"     ,&FEB_v1::setGbtTrackMode)
    .def("gbtTrackMode"        ,&FEB_v1::gbtTrackMode)
    .def("setGbtTermEport"     ,&FEB_v1::setGbtTermEport)
    .def("gbtTermEport"        ,&FEB_v1::gbtTermEport)
    .def("setGbt80MHzClkEport" ,&FEB_v1::setGbt80MHzClkEport)
    .def("gbt80MHzClkEport"    ,&FEB_v1::gbt80MHzClkEport)
    .def("setGbtDLLEport"      ,&FEB_v1::setGbtDLLEport)
    .def("gbtDLLEport"         ,&FEB_v1::gbtDLLEport)
    .def("setGbtEnableEport"   ,&FEB_v1::setGbtEnableEport)
    .def("gbtEnableEport"      ,&FEB_v1::gbtEnableEport)
    .def("setGbtClockStrength"   ,&FEB_v1::setGbtClockStrength)
    .def("gbtClockStrength"      ,&FEB_v1::gbtClockStrength)
    .def("gbtStatus"           ,&FEB_v1::gbtStatus)
    .def("gbtDLLReset"         ,&FEB_v1::gbtDLLReset)
    .def("gbtAcknowledgeConfig",&FEB_v1::gbtAcknowledgeConfig)

    .def("setOutputEport"      ,setOutputEport1)
    .def("latencyEport"        ,latencyEport1)
    .def("clockPhaseEport"     ,clockPhaseEport1)

    .def("setOutputEport"      ,setOutputEport2)
    .def("latencyEport"        ,latencyEport2)
    .def("clockPhaseEport"     ,clockPhaseEport2)
   
    .def("data",&FEB_v1::data,return_value_policy<reference_existing_object>())
    ;
  
  StatusCode (SeqPGA::*spiwrite_1)(unsigned int, unsigned int) = (&SeqPGA::spiWrite);
  StatusCode (SeqPGA::*spiwrite_2)(unsigned int, unsigned int, PyObject*) = (&SeqPGA::spiWrite);

  unsigned int (SeqPGA::*spiread_1)(unsigned int) = (&SeqPGA::spiRead);
  PyObject* (SeqPGA::*spiread_2)(unsigned int, unsigned int) = (&SeqPGA::spiRead);

  StatusCode (SeqPGA::*i2cwrite_1)() = (&SeqPGA::i2cWrite);
  StatusCode (SeqPGA::*i2cwrite_2)(unsigned long int, unsigned long int) = (&SeqPGA::i2cWrite);
  StatusCode (SeqPGA::*i2cread_1)() = (&SeqPGA::i2cRead);
  unsigned long int (SeqPGA::*i2cread_2)(unsigned long int) = (&SeqPGA::i2cRead);

  class_<SeqPGA, bases <Element> >("SeqPGA")
    .def("usb",&SeqPGA::usb,return_value_policy<reference_existing_object>())
    .def("spi",&SeqPGA::spi,return_value_policy<reference_existing_object>())
    .def("i2c",&SeqPGA::i2c,return_value_policy<reference_existing_object>())
    .def("reg",&SeqPGA::reg,return_value_policy<reference_existing_object>())

    .def("setupReg",&SeqPGA::setupReg,return_value_policy<reference_existing_object>())

    .def("testSequence"    ,&SeqPGA::testSequence)
    .def("setExtTrig"      ,&SeqPGA::setExtTrig)
    .def("extTrig"         ,&SeqPGA::extTrig)
    

    .def("setSpiGBTSCA"  ,&SeqPGA::setSpiGBTSCA)
    .def("spiGBTSCA"     ,&SeqPGA::spiGBTSCA)
    .def("setSpiEnable"  ,&SeqPGA::setSpiEnable)
    .def("spiEnable"     ,&SeqPGA::spiEnable)
    .def("setLedEnable"  ,&SeqPGA::setLedEnable)
    .def("ledEnable"     ,&SeqPGA::ledEnable)
    //    .def("setSpiDataTx"  ,&SeqPGA::setSpiDataTx)
    //    .def("spiDataTx"     ,&SeqPGA::spiDataTx)
    //    .def("setSpiDataRx"  ,&SeqPGA::setSpiDataRx)
    //    .def("spiDataRx"     ,&SeqPGA::spiDataRx) 
    .def("setSpiAdd"     ,&SeqPGA::setSpiAdd)
    .def("spiAdd"        ,&SeqPGA::spiAdd) 
    .def("setSpiSubAdd"  ,&SeqPGA::setSpiSubAdd)
    .def("spiSubAdd"      ,&SeqPGA::spiSubAdd)
    .def("spiWrite"          ,spiwrite_1)
    .def("spiWrite"          ,spiwrite_2)
    .def("spiRead"           ,spiread_1)
    .def("spiRead"           ,spiread_2)

    .def("addI2cReg"       ,&SeqPGA::addI2cReg,return_value_policy<reference_existing_object>())
    .def("masterI2cReg",&SeqPGA::masterI2cReg,return_value_policy<reference_existing_object>())

    .def("setI2cGBTSCA"    ,&SeqPGA::setI2cGBTSCA)
    .def("i2cGBTSCA"       ,&SeqPGA::i2cGBTSCA)
    .def("setI2cBuffer"    ,&SeqPGA::setI2cBuffer)
    .def("buffer"          ,&SeqPGA::i2cBuffer)
    .def("i2cData"            ,&SeqPGA::i2cData)
    .def("setI2cAdd"       ,&SeqPGA::setI2cAdd)
    .def("i2cAdd"             ,&SeqPGA::i2cAdd) 
    .def("setI2cSubAdd"    ,&SeqPGA::setI2cSubAdd)
    .def("i2cSubAdd"          ,&SeqPGA::i2cSubAdd)
    .def("i2cWrite"        ,i2cwrite_1)
    .def("i2cWrite"        ,i2cwrite_2)
    .def("i2cRead"         ,i2cread_1)
    .def("i2cRead"         ,i2cread_2)
   ;
  
 class_<CU_v1, bases <Element> >("CU_v1")
   .def("fePga"           ,&CU_v1::fePga,return_value_policy<reference_existing_object>())
   .def("readFifo"    ,&CU_v1::readFifo)

 ;

 StatusCode (FePGA::*spiwrite_3)(unsigned int, unsigned int) = (&FePGA::spiWrite);
 StatusCode (FePGA::*spiwrite_4)(unsigned int, unsigned int, PyObject*) = (&FePGA::spiWrite);

 unsigned int (FePGA::*spiread_3)(unsigned int) = (&FePGA::spiRead);
 PyObject* (FePGA::*spiread_4)(unsigned int, unsigned int) = (&FePGA::spiRead);


 class_<FePGA, bases <Element> >("FePGA")
   .def("usb",&FePGA::usb,return_value_policy<reference_existing_object>())
   .def("spi",&FePGA::spi,return_value_policy<reference_existing_object>())
   .def("i2c",&FePGA::i2c,return_value_policy<reference_existing_object>())
   //.def("reg",&FePGA::reg,return_value_policy<reference_existing_object>())
   .def("setupReg",&FePGA::setupReg,return_value_policy<reference_existing_object>())
   // .def("testSequence"    ,&FePGA::testSequence)
   // .def("setExtTrig"      ,&FePGA::setExtTrig)
   // .def("extTrig"         ,&FePGA::extTrig)
   .def("setSpiGBTSCA"  ,&FePGA::setSpiGBTSCA)
   // .def("spiGBTSCA"     ,&FePGA::spiGBTSCA)
   .def("setSpiAdd"     ,&FePGA::setSpiAdd)
   // .def("spiAdd"        ,&FePGA::spiAdd) 
   // .def("setSpiSubAdd"  ,&FePGA::setSpiSubAdd)
   // .def("spiSubAdd"      ,&FePGA::spiSubAdd)
   .def("spiWrite"          ,spiwrite_3)
   .def("spiWrite"          ,spiwrite_4)

   .def("spiRead"           ,spiread_3) //This is needed by readfifo
   .def("spiRead"           ,spiread_4)
   // .def("addI2cReg"       ,&FePGA::addI2cReg,return_value_policy<reference_existing_object>())
   //.def("masterI2cReg",&FePGA::masterI2cReg,return_value_policy<reference_existing_object>())
   // .def("setI2cGBTSCA"    ,&FePGA::setI2cGBTSCA)
   // .def("i2cGBTSCA"       ,&FePGA::i2cGBTSCA)
   // .def("setI2cBuffer"    ,&FePGA::setI2cBuffer)
   // .def("buffer"          ,&FePGA::i2cBuffer)
   // .def("i2cData"            ,&FePGA::i2cData)
   // .def("setI2cAdd"       ,&FePGA::setI2cAdd)
   // .def("i2cAdd"             ,&FePGA::i2cAdd) 
   // .def("setI2cSubAdd"    ,&FePGA::setI2cSubAdd)
   // .def("i2cSubAdd"          ,&FePGA::i2cSubAdd)
   // .def("i2cWrite"        ,i2cwrite_1)
   //  .def("i2cWrite"        ,i2cwrite_2)
   // .def("i2cRead"         ,i2cread_1)
   //  .def("i2cRead"         ,i2cread_2)
   ;
    

  enum_<UsbFTMLInterface::WordSize>("WordSize")
    .value("U8", UsbFTMLInterface::WS_Byte)
    .value("U16", UsbFTMLInterface::WS_Word)
    .value("U32", UsbFTMLInterface::WS_DWord)
   ;

  StatusCode (UsbFTMLInterface::*write_1)(unsigned long int, boost::python::list) = (&UsbFTMLInterface::write);
  StatusCode (UsbFTMLInterface::*write_2)(IOdata*) = (&UsbFTMLInterface::write);
  StatusCode (UsbFTMLInterface::*read_1)(unsigned long int,unsigned long int, boost::python::list&) = (&UsbFTMLInterface::read);
  StatusCode (UsbFTMLInterface::*read_2)(IOdata*) = (&UsbFTMLInterface::read);

  class_<UsbFTMLInterface, bases <Element> > ("UsbFTMLInterface")
    .def("init"           ,&UsbFTMLInterface::init)
    .def("setSerialNum"   ,&UsbFTMLInterface::setSerialNum)
    .def("setDeviceDesc"  ,&UsbFTMLInterface::setDeviceDesc)
    .def("serialNum"      ,&UsbFTMLInterface::serialNum)
    .def("deviceDesc"     ,&UsbFTMLInterface::deviceDesc)
    .def("setWordSize"    ,&UsbFTMLInterface::setWordSize)
    .def("wordSize"       ,&UsbFTMLInterface::wordSize)
    .def("close"          ,&UsbFTMLInterface::close)
    .def("setLatencyTimer",&UsbFTMLInterface::setLatencyTimer)
    .def("latencyTimer"   ,&UsbFTMLInterface::latencyTimer)
    .def("setTimeOut"     ,&UsbFTMLInterface::setTimeOut)
    .def("txTimeOut"      ,&UsbFTMLInterface::txTimeOut)
    .def("rxTimeOut"      ,&UsbFTMLInterface::rxTimeOut)
    .def("setBuffer"      ,&UsbFTMLInterface::setBuffer)
    .def("txBuffer"       ,&UsbFTMLInterface::txBuffer)
    .def("rxBuffer"       ,&UsbFTMLInterface::rxBuffer)
    .def("resetMode"         ,&UsbFTMLInterface::resetMode)
    .def("purgeBuffers"      ,&UsbFTMLInterface::purgeBuffers)
    .def("setSynchronousMode",&UsbFTMLInterface::setSynchronousMode)
    .def("write"          ,write_1)
    .def("write"          ,write_2)
    .def("read"           ,read_1)
    .def("read"           ,read_2)
    ;
 
  class_<UsbMLSpiBus, bases <Element> >("UsbMLSpiBus")
    ;
  
  class_<UsbMLI2cBus, bases <Element> >("UsbMLI2cBus")
    ;
  
  void (ICPhaser::*setPhasex2)(unsigned char, unsigned char) = (&ICPhaser::setPhase);
  void (ICPhaser::*setPhasex4)(unsigned char, unsigned char,
                   unsigned char, unsigned char) = (&ICPhaser::setPhase);

  class_<ICPhaser, bases <Element> >("ICPhaser")
    .def("setPhase",setPhasex2)
    .def("setPhase",setPhasex4)
    .def("setAddress",&ICPhaser::setAddress)
    .def("address",&ICPhaser::address)
    .def("status",&ICPhaser::status)
    .def("reset",&ICPhaser::reset)
    .def("read" ,&ICPhaser::read)
    .def("write",&ICPhaser::write)
    .def("regConfig"  ,&ICPhaser::regConfig,
     return_value_policy<reference_existing_object>())
    .def("regStatus"  ,&ICPhaser::regStatus,
     return_value_policy<reference_existing_object>())
    ;

  //    class_<TestUSB, bases<Processus> > ("TestUSB")
  //    ;  

  class_<TestSPI, bases<Processus> > ("TestSPI")
    .def("setAddress",     &TestSPI::setAddress)
    .def("setSubAddress",  &TestSPI::setSubAddress) 
    ;  

  class_<TestI2C, bases<Processus> > ("TestI2C")
    .def("setAddress",     &TestI2C::setAddress)
    .def("setSubAddress",  &TestI2C::setSubAddress) 
    ;  

  class_<Acquisition, bases<Processus> > ("Acquisition")
    .def("setDepth"  , &Acquisition::setDepth)
    .def("setTrigger", &Acquisition::setTrigger) 
    ;  

}