FEB_v1.cpp

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// $Id: $
// Include files


// local
#include "FEB_v1.h"
#include "SeqPGA.h"

//-----------------------------------------------------------------------------
// Implementation file for class : FEB_v1
//
// 2006-10-23 :
//-----------------------------------------------------------------------------

//=============================================================================
// Standard constructor, initializes variables
//=============================================================================
FEB_v1::FEB_v1(  ) {
  setName("FEB_v1");
  setType("FEB_v1");
  add(Attrib::ELEMENT); add (Attrib::HARDWARE);

  m_fifoDepth = 1024;

  m_feAddress[0] = 1;
  m_feAddress[1] = 2;
  m_feAddress[2] = 5;
  m_feAddress[3] = 6;
  m_feAddress[4] = 9;
  m_feAddress[5] = 10;
  m_feAddress[6] = 13;
  m_feAddress[7] = 14;

  m_seqAddress   = 17 ; 

  m_gbtAddress[0] = 1;
  m_gbtAddress[1] = 2;
  m_gbtAddress[2] = 3;
  m_gbtAddress[3] = 4;
    
  m_icecalAddress[0] = 3;
  m_icecalAddress[1] = 4;
  m_icecalAddress[2] = 7;
  m_icecalAddress[3] = 8;
  m_icecalAddress[4] = 11;
  m_icecalAddress[5] = 12;
  m_icecalAddress[6] = 15;
  m_icecalAddress[7] = 16;
    
  m_fifoSpyAddress[0] = 20;
  m_fifoSpyAddress[1] = 21;
  m_fifoSpyAddress[2] = 22;

  m_fifoInjectAddress[0] = 23;
  m_fifoInjectAddress[1] = 24;
  m_fifoInjectAddress[2] = 25;

  m_fifoLLTAddress[0] = 26;
  m_fifoLLTAddress[1] = 27;
  m_fifoLLTAddress[2] = 29;

  m_fifoTrigAddress[0] = 10;
  m_fifoTrigAddress[1] = 11;
  m_fifoTrigAddress[2] = 17;

  m_seqPga =new SeqPGA();
  m_seqPga->setName("SeqPGA");
  addChild(m_seqPga);

  m_fifo[0] = new unsigned int[m_fifoDepth];
  m_fifo[1] = new unsigned int[m_fifoDepth];
  m_fifo[2] = new unsigned int[m_fifoDepth];

  m_ch[0] = new int[m_fifoDepth];
  m_ch[1] = new int[m_fifoDepth];
  m_ch[2] = new int[m_fifoDepth];
  m_ch[3] = new int[m_fifoDepth];

  for (int i = 0; i<3; ++i){
    m_ramInj[i] = new RAM();
    m_ramSpy[i] = new RAM();
    seqPga()->usb()->addChild(m_ramInj[i]);
    seqPga()->usb()->addChild(m_ramSpy[i]);
    m_ramInj[i]->setAddress(13); // for debug
    m_ramSpy[i]->setAddress(m_fifoSpyAddress[i]);
    m_ramInj[i]->setSize(16, m_fifoDepth);
    m_ramSpy[i]->setSize(16, m_fifoDepth);
  }

  m_fifoUsbTest = new RAM();
  m_fifoUsbTest->setAddress(3);
  m_fifoUsbTest->setSize(16,256);
  m_fifoUsbTest->setName("FifoUsbTest");
  seqPga()->usb()->addChild(m_fifoUsbTest);

  m_data = new Data();
  for (int ch=0; ch<32; ++ch){
    m_data->addDataStream("ch"+itos(ch), "Channel "+itos(ch));
  }
  m_data->addDataStream("llt_fifo0", "llt_fifo0");
  m_data->addDataStream("llt_fifo1", "llt_fifo1");
  
}
//=============================================================================
// Destructor
//=============================================================================
FEB_v1::~FEB_v1() {
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::readFifo( int  add, int subadd, unsigned int *fifo){
  m_seqPga->spiRead(subadd, m_fifoDepth, fifo);
}

//=============================================================================
// 
//=============================================================================

void FEB_v1::readFifoSpyFE( int fe, int dump=0){
   
  m_seqPga->setSpiAdd(m_feAddress[fe]);

  debug("Reading fifo 0","FEB_v1::readFifoSpyFE");
  readFifo(m_feAddress[fe], m_fifoSpyAddress[0], m_fifo[0]);
  debug("Reading fifo 1","FEB_v1::readFifoSpyFE");
  readFifo(m_feAddress[fe], m_fifoSpyAddress[1], m_fifo[1]);
  debug("Reading fifo 2","FEB_v1::readFifoSpyFE");
  readFifo(m_feAddress[fe], m_fifoSpyAddress[2], m_fifo[2]);
  
  char buffer[100];
  
  int depth = testDuration(fe);
  for (int ch=0; ch<4; ++ch){
    m_data->clear(4*fe+ch);
  }
  
  for (int d=0; d<depth; ++d){ 
    m_ch[0][d]=m_fifo[0][d]&0x0FFF;
    m_ch[1][d]=(((m_fifo[0][d]&0xF000)>>12)+((m_fifo[1][d]&0x00FF)<<4))&0xFFF;
    m_ch[2][d]=(((m_fifo[1][d]&0xFF00)>>8)+((m_fifo[2][d]&0x000F)<<8))&0xFFF;
    m_ch[3][d]=(m_fifo[2][d]&0xFFF0)>>4;
    for (int ch=0; ch<4; ++ch){
      m_data->dataFill(4*fe+ch , m_ch[ch][d]);
    }
    if (dump>0) {
      sprintf(buffer,"%5d : %5d %5d %5d %5d  |  %5d %5d %5d", d,
          m_ch[0][d], m_ch[1][d], m_ch[2][d], m_ch[3][d],
          m_fifo[0][d], m_fifo[1][d], m_fifo[2][d]);
      info(buffer,"FEB_v1::readFifoSpyFE");
    }
  }
}

//=============================================================================
// 
//=============================================================================

void FEB_v1::readFifoLLTFE( int fe, int dump=0){

  m_seqPga->setSpiGBTSCA (false) ;
  info("Reading fifo 0","FEB_v1::readFifoLLTFE");
  readFifo(m_feAddress[fe], m_fifoLLTAddress[0], m_fifo[0]);
  info("Reading fifo 1","FEB_v1::readFifoLLTFE");
  readFifo(m_feAddress[fe], m_fifoLLTAddress[1], m_fifo[1]);
  info("Reading fifo 2","FEB_v1::readFifoLLTFE");
  readFifo(m_feAddress[fe], m_fifoLLTAddress[2], m_fifo[2]);
  
  char buffer[100];
  
  int depth = testDuration(fe);

  for (int ch=0; ch<4; ++ch){
    m_data->clear(4*fe+ch);
  }
  
  for (int d=0; d<depth; ++d){ 
    m_ch[0][d]=m_fifo[0][d]&0x3FF;
    m_ch[1][d]=(((m_fifo[0][d])>>10)+((m_fifo[1][d]&0xF)<<6))&0x3FF;
    m_ch[2][d]=((m_fifo[1][d]&0x3FF0)>>4);
    m_ch[3][d]=m_fifo[2][d]&0x3FF;
    for (int ch=0; ch<4; ++ch){
      m_data->dataFill(4*fe+ch , m_ch[ch][d]);
    }
    if (dump>0) {
      sprintf(buffer,"%5d : %5d %5d %5d %5d  |  %5d %5d %5d", d,
          m_ch[0][d], m_ch[1][d], m_ch[2][d], m_ch[3][d],
          m_fifo[0][d], m_fifo[1][d], m_fifo[2][d]);
      info(buffer,"FEB_v1::readFifoLLTFE");
    }
  }
}


//=============================================================================
// 
//=============================================================================

void FEB_v1::readFifoLLT(int dump=0){

  m_seqPga->setSpiGBTSCA (false) ;
  info("Reading fifo 0","FEB_v1::readFifoLLT");
  readFifo(m_seqAddress, m_fifoTrigAddress[0], m_fifo[0]);
  info("Reading fifo 1","FEB_v1::readFifoLLT");
  readFifo(m_seqAddress, m_fifoTrigAddress[1], m_fifo[1]);
  info("Reading fifo 2","FEB_v1::readFifoLLT");
  readFifo(m_seqAddress, m_fifoTrigAddress[2], m_fifo[2]);
  
  char buffer[100];
  int depth = testDuration(-1);

  m_data->clear(32);
  m_data->clear(33);
  
  for (int d=0; d<depth; ++d){
    m_data->dataFill(32, m_fifo[0][d]);
    m_data->dataFill(33, m_fifo[1][d]);
    if (dump>0) {
      sprintf(buffer,
          "%5d : ETtot=%4d ETmax=%4d [%2d] Mult=%2d Bx=%4d (%4d) | %5d %5d %5d",
          d,
          (m_fifo[0][d])&0x7FF, (m_fifo[1][d])&0x3FF, 
          (m_fifo[0][d]>>11)&0x1F,(m_fifo[1][d]>>10)&0x3F, 
          (m_fifo[2][d]>>10)&0x3F,(m_fifo[2][d])&0x3FF,
          m_fifo[0][d], m_fifo[1][d], m_fifo[2][d]);
      info(buffer,"FEB_v1::readFifoLLT");
    }
  }
}

//=============================================================================
// 
//=============================================================================

void FEB_v1::readFifoInjectFE( int fe, int dump=0){
  setInjectModeFE(fe, false);
  m_seqPga->setSpiGBTSCA (false);
  info("Reading fifo 0","FEB_v1::readFifoInjectFE");
  readFifo(m_feAddress[fe], m_fifoInjectAddress[0], m_fifo[0]);
  info("Reading fifo 1","FEB_v1::readFifoInjectFE");
  readFifo(m_feAddress[fe], m_fifoInjectAddress[1], m_fifo[1]);
  info("Reading fifo 2","FEB_v1::readFifoInjectFE");
  readFifo(m_feAddress[fe], m_fifoInjectAddress[2], m_fifo[2]);
  
  char buffer[100];
  int depth = testDuration(fe);
  for (int d=0; d<depth; ++d){ 
    m_ch[0][d]=m_fifo[0][d]&0x0FFF;
    m_ch[1][d]=(((m_fifo[0][d]&0xF000)>>12)+((m_fifo[1][d]&0x00FF)<<4))&0xFFF;
    m_ch[2][d]=(((m_fifo[1][d]&0xFF00)>>8)+((m_fifo[2][d]&0x000F)<<8))&0xFFF;
    m_ch[3][d]=((m_fifo[2][d]&0xFFF0)>>4)&0xFFF;
    if (dump>0) {
      sprintf(buffer,"%5d : %5d %5d %5d %5d  |  %5d %5d %5d", d,
          m_ch[0][d], m_ch[1][d], m_ch[2][d], m_ch[3][d],
          m_fifo[0][d], m_fifo[1][d], m_fifo[2][d]);
      info(buffer,"FEB_v1::readFifoInjectFE");
    }
  }
  setInjectModeFE(fe, true);
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::writeFifoSpyFE( int fe){
  setSpyModeFE(fe, false);
  int depth = testDuration(fe);
  for (int d=0; d<depth; ++d){
    m_fifo[0][d]=d;
    m_fifo[1][d]=d;
    m_fifo[2][d]=d; 
  }
  m_seqPga->spiWrite( m_fifoSpyAddress[0], depth, m_fifo[0] );
  m_seqPga->spiWrite( m_fifoSpyAddress[1], depth, m_fifo[1] );
  m_seqPga->spiWrite( m_fifoSpyAddress[2], depth, m_fifo[2] );
  setSpyModeFE(fe, true);
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::writeFifoLLT(){
  m_seqPga->setSpiAdd(m_seqAddress);
  int depth = testDuration(-1);
 
  for (int d=0; d<depth; ++d){
    m_fifo[0][d]=d;
    m_fifo[1][d]=d;
  }
  m_seqPga->spiWrite( m_fifoTrigAddress[0], depth, m_fifo[0] );
  m_seqPga->spiWrite( m_fifoTrigAddress[1], depth, m_fifo[1] );
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::writeFifoInjectFE( int fe, int pattern){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int depth = testDuration(fe);
 
  unsigned int buffer[depth];
  warning("Spi write mode block disabled !!!","FEB_v1::writeFifoInjectFE");        
  switch(pattern){
  default: info ("Incremented pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 1:  info ("ZERO pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 2:  info ("ZERO and ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 10:  info ("Channel 0 - Static ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 11:  info ("Channel 1 - Static ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 12:  info ("Channel 2 - Static ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 13:  info ("Channel 3 - Static ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 20:  info ("Channel 0 - 1/3 ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 21:  info ("Channel 1 - 1/3 ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 22:  info ("Channel 2 - 1/3 ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 23:  info ("Channel 3 - 1/3 ONE pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 30:  info ("Channel 0 - 1/3 0xAAA pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 31:  info ("Channel 1 - 1/3 0xAAA pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 32:  info ("Channel 2 - 1/3 0xAAA pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 33:  info ("Channel 3 - 1/3 0xAAA pattern injection","FEB_v1::writeFifoInjectFE"); break;
  case 40:  info ("Channel 0 - pow(2,i), i being the word index modulo 12","FEB_v1::writeFifoInjectFE"); break;
  case 41:  info ("Channel 1 - pow(2,i), i being the word index modulo 12","FEB_v1::writeFifoInjectFE"); break;
  case 42:  info ("Channel 2 - pow(2,i), i being the word index modulo 12","FEB_v1::writeFifoInjectFE"); break;
  case 43:  info ("Channel 3 - pow(2,i), i being the word index modulo 12","FEB_v1::writeFifoInjectFE"); break;
  case 100:  info ("Pulse mode - clock running at 40/16 MHz","FEB_v1::writeFifoInjectFE"); break;
  }

  info("Injection FIFO 0","FEB_v1::writeFifoInjectFE");        
  for (int i=0; i<depth; ++i){
    switch (pattern){
    default: buffer[i]=(i+((i+1)<<12))&0xFFFF; break;
    case 1:   buffer[i]=(0)&0xFFFF; break;
    case 2:   buffer[i]=0xFFFF*(i&1); break;
    case 10:  buffer[i]=0x0FFF; break;
    case 11:  buffer[i]=0xF000; break;
    case 12:  buffer[i]=0; break;
    case 13:  buffer[i]=0; break;
    case 20:  i%4==0?buffer[i]=0x0FFF:buffer[i]=0; break;
    case 21:  i%4==0?buffer[i]=0xF000:buffer[i]=0; break;
    case 22:  buffer[i]=0; break;
    case 23:  buffer[i]=0; break;
    case 30:  i%4==0?buffer[i]=0x0AAA:buffer[i]=0; break;
    case 31:  i%4==0?buffer[i]=0xA000:buffer[i]=0; break;
    case 32:  buffer[i]=0; break;
    case 33:  buffer[i]=0; break;
    case 40:  buffer[i]=int(pow(2,i%12)); break;
    case 41:  buffer[i]=(int(pow(2,i%12))<<12)&0xFFFF; break;
    case 42:  buffer[i]=0; break;
    case 43:  buffer[i]=0; break;
    case 50:  buffer[i]=1; break;
    case 51:  buffer[i]=2; break;
    case 52:  buffer[i]=2048; break;
    case 100: ((i>>4)&0x1)==0 ? buffer[i]=1 : buffer[i]=0; break;
    }
   }
  for (int i=0; i<depth; ++i){
    m_seqPga->spiWrite( m_fifoInjectAddress[0], buffer[i]);
  }
  
  info("Injection FIFO 1","FEB_v1::writeFifoInjectFE");        
  for (int i=0; i<depth; ++i){ 
    switch(pattern){
    default:  buffer[i]=((((i+1)>>4)&0xFF)+((i+2)<<8))&0xFFFF; break;
    case 1:   buffer[i]=(0)&0xFFFF; break;
    case 2:   buffer[i]=0xFFFF*(i&1); break;
    case 10:  buffer[i]=0; break;
    case 11:  buffer[i]=0x00FF; break;
    case 12:  buffer[i]=0xFF00; break;
    case 13:  buffer[i]=0; break;
    case 20:  buffer[i]=0; break;
    case 21:  i%4==0?buffer[i]=0x00FF:buffer[i]=0; break;
    case 22:  i%4==0?buffer[i]=0xFF00:buffer[i]=0; break;
    case 23:  buffer[i]=0; break;
    case 30:  buffer[i]=0; break;
    case 31:  i%4==0?buffer[i]=0x00AA:buffer[i]=0; break;
    case 32:  i%4==0?buffer[i]=0xAA00:buffer[i]=0; break;
    case 33:  buffer[i]=0; break;
    case 40:  buffer[i]=0; break;
    case 41:  buffer[i]=(int(pow(2,i%12))>>4)&0xFF; break;
    case 42:  buffer[i]=(int(pow(2,i%12))<<8)&0xFFFF; break;
    case 43:  buffer[i]=0; break;
    case 50:  buffer[i]=0; break;
    case 51:  buffer[i]=0; break;
    case 52:  buffer[i]=0; break;
    case 100: buffer[i]=0; break;
   }
   }
  for (int i=0; i<depth; ++i){
    m_seqPga->spiWrite( m_fifoInjectAddress[1], buffer[i]);
  }
  
  info("Injection FIFO 2","FEB_v1::writeFifoInjectFE");        
  for (int i=0; i<depth; ++i){ 
    switch(pattern){
    default:  buffer[i]=((((i+2)>>8)&0xF)+((i+3)<<4))&0xFFFF; break;
    case 1:   buffer[i]=(0)&0xFFFF; break;
    case 2:   buffer[i]=0xFFFF*(i&1); break;
    case 10:  buffer[i]=0; break;
    case 11:  buffer[i]=0; break;
    case 12:  buffer[i]=0x000F; break;
    case 13:  buffer[i]=0xFFF0; break;
    case 20:  buffer[i]=0; break;
    case 21:  buffer[i]=0; break;
    case 22:  i%4==0?buffer[i]=0x000F:buffer[i]=0; break;
    case 23:  i%4==0?buffer[i]=0xFFF0:buffer[i]=0; break;
    case 30:  buffer[i]=0; break;
    case 31:  buffer[i]=0; break;
    case 32:  i%4==0?buffer[i]=0x000A:buffer[i]=0; break;
    case 33:  i%4==0?buffer[i]=0xAAA0:buffer[i]=0; break;
    case 40:  buffer[i]=0; break;
    case 41:  buffer[i]=0; break;
    case 42:  buffer[i]=(int(pow(2,i%12))>>8)&0xF; break;
    case 43:  buffer[i]=(int(pow(2,i%12))<<4)&0xFFFF; break;
    case 50:  buffer[i]=0; break;
    case 51:  buffer[i]=0; break;
    case 52:  buffer[i]=0; break;
    case 100: buffer[i]=0; break;    
    }
   }  
  for (int i=0; i<depth; ++i){
    m_seqPga->spiWrite( m_fifoInjectAddress[2], buffer[i]);
  }
}
//=============================================================================
// 
//=============================================================================
void FEB_v1::writeDataFifoInjectFE( int fe, int *ch0, int* ch1, int* ch2, int* ch3){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int depth = testDuration(fe);
  
  info("Injection FIFO 0","FEB_v1::readFifoInjectFE");        
  for (int i=0; i<depth; ++i){m_fifo[0][i]=(ch0[i]&0xFFF)+((ch1[i]<<12)&0xF000);}
  m_seqPga->spiWrite(m_fifoInjectAddress[0], depth, m_fifo[0]);
  info("Injection FIFO 1","FEB_v1::readFifoInjectFE");        
  for (int i=0; i<depth; ++i){m_fifo[1][i]=((ch1[i]>>4)&0xFF)+((ch2[i]<<8)&0xFF00);}
  m_seqPga->spiWrite(m_fifoInjectAddress[1], depth, m_fifo[1]);
  info("Injection FIFO 2","FEB_v1::readFifoInjectFE");        
  for (int i=0; i<depth; ++i){m_fifo[2][i]=((ch2[i]>>8)&0xF)+((ch3[i]<<4)&0xFFF0);}
  m_seqPga->spiWrite(m_fifoInjectAddress[2], depth, m_fifo[2]);
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::writeFifoLLTFE( int fe){
  warning("This function is commented.");
  int depth = testDuration(fe);
  /*
  m_seqPga->setSpiAdd( m_feAddress[fe] );
  m_seqPga -> setSpiSubAdd( m_fifoLLTAddress[0] );  
  info("LLT FE FIFO 0","FEB_v1::readFifoLLTFE");        
  for (int d=0; d<depth; ++d){ 
    m_seqPga -> setSpiDataTx(d);
    m_seqPga -> transmitSpi();
  }
  m_seqPga -> setSpiSubAdd( m_fifoLLTAddress[1] );
  for (int d=0; d<depth; ++d){ 
    m_seqPga -> setSpiDataTx(d);
    m_seqPga -> transmitSpi();
  }
  m_seqPga -> setSpiSubAdd( m_fifoLLTAddress[2] );
  for (int d=0; d<depth; ++d){ 
    m_seqPga -> setSpiDataTx(d);
    m_seqPga -> transmitSpi();
    }
*/
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::resetFifoSpyFE(int fe){  
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  StatusCode val = (m_seqPga->spiWrite(12,0));
  debug("Reset FIFO Spy FE "+itos(fe),"FEB_v1::resetFifoSpyFE");
  return val;
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::resetFifoInjectFE(int fe){  
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  StatusCode val = (m_seqPga->spiWrite(13,0));
  info("Reset FIFO Inject FE "+itos(fe),"FEB_v1::resetFifoInjectFE");
  return val;
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::resetFE(int fe){  
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  StatusCode val = (m_seqPga->spiWrite(11,0));
  info("Reset FE "+itos(fe),"FEB_v1::resetFE");
  return val;
}

//=============================================================================
// 
//=============================================================================
int FEB_v1::statusRegister(int fe){  
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(10));
  info("Status register FE "+itos(fe)+": "+itos(val),"FEB_v1::statusRegister");
  return val;
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::setTestDuration(int duration){
  m_seqPga->setSpiAdd(m_seqAddress);
  int data = m_seqPga->spiRead(12);
  data &= 0xFC00;
  data |= (duration&0x3FF);
  if (m_seqPga->spiWrite(12,data).isFailure()){
    warning("Cannot write test sequence duration for Seq pga ","FEB_v1::setTestDuration");
    return StatusCode::FAILURE;
  }
  for (int fe=0; fe<8; ++fe){
    m_seqPga->setSpiAdd(m_feAddress[fe]);
    data = m_seqPga->spiRead(3);
    data &= 0xFC00;
    data |= (duration&0x3FF);
    if (m_seqPga->spiWrite(3,data).isFailure()){
      warning("Cannot write test sequence duration for FE pga "+ itos(fe),
          "FEB_v1::setTestDuration");
      return StatusCode::FAILURE;
    }
  }
  return StatusCode::SUCCESS;
}

//=============================================================================
// 
//=============================================================================
int FEB_v1::testDuration(int fpga){
  int val=-1;
  if (fpga==-1){
    m_seqPga->setSpiAdd(m_seqAddress);
    val = (m_seqPga->spiRead(12))&0x3FF;
    debug("Test Length Seq: "+itos(val),"FEB_v1::testDuration");
    m_fifoDepth = val;
    return val;
  }
  else {
    m_seqPga->setSpiAdd(m_feAddress[fpga]);
    val = (m_seqPga->spiRead(3))&0x3FF;
    debug("Test Length FE: "+itos(fpga)+" "+itos(val),"FEB_v1::testDuration");
    m_fifoDepth = val;
    return val;
  }
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::setStopInjLoop(bool stoploop){
  m_seqPga->setSpiAdd(m_seqAddress);
  int data = m_seqPga->spiRead(12);
  data &= 0x0FFF;
  data |= (stoploop<<12);
  if (m_seqPga->spiWrite(12,data).isFailure()){
    warning("Cannot write test sequence loop for Seq pga ","FEB_v1::setStopInjLoop");
    return StatusCode::FAILURE;
  }
  for (int fe=0; fe<8; ++fe){
    m_seqPga->setSpiAdd(m_feAddress[fe]);
    data = m_seqPga->spiRead(3);
    data &= 0x0FFF;
    data |= (stoploop<<12);
    if (m_seqPga->spiWrite(3,data).isFailure()){
      warning("Cannot write test loop for FE pga "+ itos(fe),
          "FEB_v1::setStopInjLoop");
      return StatusCode::FAILURE;
    }
  }
  return StatusCode::SUCCESS;
}

//=============================================================================
// 
//=============================================================================
bool FEB_v1::stopInjLoop(int fpga){
  bool val;
  if (fpga==-1){
    m_seqPga->setSpiAdd(m_seqAddress);
    val = (m_seqPga->spiRead(12)>>12)&0x1;
    info("Test Length Seq stop Loop: "+itos(val),"FEB_v1::stopInjLoop");
    return val;
  }
  else {
    m_seqPga->setSpiAdd(m_feAddress[fpga]);
    val = (m_seqPga->spiRead(3)>>12)&0x1;
    info("Test Length FE stop Loop : "+itos(fpga)+" "+itos(val),"FEB_v1::stopInjLoop");
    return val;
  }
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::setProbeEnable( int fe, bool enable){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = m_seqPga->spiRead(2);
  if (enable) {
    info("Enabling Seq PGA probes","FEB_v1::setProbeEnable");
    val |= 0xF;
  }
  else {
    info("Disabling Seq PGA probes","FEB_v1::setProbeEnable");
    val &=0xFFF0;
  }
  return m_seqPga->spiWrite(2,val);
}

//=============================================================================
// 
//=============================================================================
void FEB_v1::probeEnable(){
  for (int fe = 0; fe<8; ++fe){
    m_seqPga->setSpiAdd(m_feAddress[fe]);
    int val = (m_seqPga->spiRead(2))&0xF;
    info("Probe Enable FE "+itos(fe)+": "+itos(val),"FEB_v1::probeEnable");
  }
}

//=============================================================================
// 
//=============================================================================
StatusCode FEB_v1::setSpareForTrigEnable( int fe, int enable){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = m_seqPga->spiRead(2) & 0xFF0F;
  info("SetSpareForTrig FE "+itos(fe)+" : "+itos(enable),"FEB_v1::setSpareForTrigEnable");
  val |= (enable<<4)&0xF0;
  return m_seqPga->spiWrite(2,val);
}

//=============================================================================
// 
//=============================================================================
int FEB_v1::spareForTrigEnable(int fe){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = ((m_seqPga->spiRead(2))&0xF0)>>4;
  info("spareForTrigEnable for FE "+itos(fe)+" : "+itos(val),"FEB_v1::probeEnable");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setSpyModeSeq( bool value ){
  m_seqPga->setSpiAdd(m_seqAddress);
  unsigned int data=m_seqPga->spiRead(1);
  if (value)  data |= 32  ;
  else        data &= ~32 ;
  return m_seqPga->spiWrite(1,data);
}

bool FEB_v1::spyModeSeq( ){
  m_seqPga->setSpiAdd(m_seqAddress);
  int val = m_seqPga->spiRead(1)&&32 ;
  info("Spy Mode Seq: "+itos(val),"FEB_v1::spyModeSeq");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setSpyModeFE( int fe, bool value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  if (value)  data |= 1 << 14  ;
  else        data &= ~(1<<14) ;
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Spy Mode FE "+itos(fe)+" : "+itos(value)+" setup0="+itos(data),"FEB_v1::spyModeFE");
  return StatusCode::SUCCESS;
}

bool FEB_v1::spyModeFE( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>14)&1;
  info("Spy Mode FE "+itos(fe)+": "+itos(val),"FEB_v1::spyModeFE");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setThreshold( int fe, int value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  data = data & 0xc7FF;
  data += (value<<11);
  
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Threshold "+itos(fe)+": "+itos(value),"FEB_v1::setThreshold");
  return StatusCode::SUCCESS;
}

int FEB_v1::threshold( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>11)&7;
  info("threshold FE"+itos(fe)+": "+itos(val),"FEB_v1::threshold");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setLatency( int fe, int value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  data = data & 0xFF00;
  data += value&0xFF;
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Latency "+itos(fe)+": "+itos(value),"FEB_v1::setLatency");
  return StatusCode::SUCCESS;
}

int FEB_v1::latency( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1))&(0xFF);
  info("latency FE "+itos(fe)+": "+itos(val),"FEB_v1::latency");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setDisableSubtract( int fe, bool value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  data = data & 0xFDFF;
  data += (value<<9);
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Disable Subtraction "+itos(fe)+": "+itos(value),"FEB_v1::setDisableSubtract");
  return StatusCode::SUCCESS;
}

bool FEB_v1::disableSubtract( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>9)&1;
  info("Disable Subtraction FE "+itos(fe)+": "+itos(val),"FEB_v1::disableSubtract");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setEnableBXIDReset( bool value ){
  m_seqPga->setSpiAdd(m_seqAddress);
  unsigned int data=m_seqPga->spiRead(1);
  if (value) data |=  2048 ;
  else       data &= ~2048 ;
  return m_seqPga->spiWrite(1,data);
}

bool FEB_v1::enableBXIDReset( ){
  m_seqPga->setSpiAdd(m_seqAddress);
  int data=m_seqPga->spiRead(1);
  return ( data >>11 ) & 1;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setOldSubtract( int fe, bool value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  data = data & 0xFEFF;
  data += (value<<8);
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Old Subtraction mode "+itos(fe)+": "+itos(value),"FEB_v1::setOldSubtract");
  return StatusCode::SUCCESS;
}

bool FEB_v1::oldSubtract( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>8)&1;
  info("Old Subtract "+itos(fe)+": "+itos(val),"FEB_v1::oldSubtract");
  return val;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setInjectModeFE( int fe, bool value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  if (value)  data |= 1 << 10 ;
  else        data &= ~(1<<10) ;
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Inject Mode FE "+itos(fe)+": "+itos(value),"FEB_v1::injectModeFE");
  return StatusCode::SUCCESS;
}

bool FEB_v1::injectModeFE( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>10)&1;
  info("Inject Mode FE "+itos(fe)+": "+itos(val),"FEB_v1::injectModeFE");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGain4( int fe, int ch, bool value ){
  if (ch>3){
    warning("try to configure a channel that does not exist.","FEB_v1::setGain4");
    return StatusCode::FAILURE;
  }
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(4+ch);
  if (value)  data |= 1 << 11 ;
  else        data &= ~(1<<11) ;
  if (m_seqPga->spiWrite(4+ch,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Gain4 FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(value),"FEB_v1::setGain4");
  return StatusCode::SUCCESS;
}

bool FEB_v1::gain4( int fe , int ch ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(4+ch)>>11)&1;
  info("Gain4 FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(val),"FEB_v1::gain4");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setPseudoADCEnable( int fe, int ch, bool value ){
  if (ch>3){
    warning("try to configure a channel that does not exist.","FEB_v1::setPseudoADCEnable");
    return StatusCode::FAILURE;
  }
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(4+ch);
  if (value)  data |= 1 << 10 ;
  else        data &= ~(1<<10) ;
  if (m_seqPga->spiWrite(4+ch,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set PseudoADCEnable "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(value),"FEB_v1::setPseudoADCEnable");
  return StatusCode::SUCCESS;
}

bool FEB_v1::pseudoADCEnable( int fe , int ch ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(4+ch)>>10)&1;
  info("Pseudo ADC Enable FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(val),"FEB_v1::pseudoADCEnable");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setPseudoPMEnable( int fe, int ch, bool value ){
  if (ch>3){
    warning("try to configure a channel that does not exist.","FEB_v1::setPseudoPMEnable");
    return StatusCode::FAILURE;
  }
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(4+ch);
  if (value)  data |= 1 << 9 ;
  else        data &= ~(1<<9) ;
  if (m_seqPga->spiWrite(4+ch,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set PseudoPMEnable FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(value),"FEB_v1::setPseudoPMEnable");
  return StatusCode::SUCCESS;
}

bool FEB_v1::pseudoPMEnable( int fe , int ch ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(4+ch)>>9)&1;
  info("Pseudo PM Enable FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(val),"FEB_v1::pseudoPMEnable");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGlobalPseudoPMEnable( int fe, bool value ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(1);
  if (value)  data |= 1 << 10 ;
  else        data &= ~(1<<10) ;
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set GlobalPseudoPMEnable FE "+itos(fe)+" : "+itos(value),"FEB_v1::setGlobalPseudoPMEnable");
  return StatusCode::SUCCESS;
}

bool FEB_v1::globalPseudoPMEnable( int fe ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(1)>>10)&1;
  info("Global Pseudo PM Enable FE "+itos(fe)+" : "+itos(val),"FEB_v1::globalPseudoPMEnable");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setClockFallingEdge( int fe, int ch, bool value ){
  if (ch>3){
    warning("try to configure a channel that does not exist.","FEB_v1::setClockFallingEdge");
    return StatusCode::FAILURE;
  }
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(4+ch);
  if (value)  data |= 1 << 8  ;
  else        data &= ~(1<<8) ;
  if (m_seqPga->spiWrite(4+ch,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Clock Falling Edge FPGA "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(value),"FEB_v1::setClockFallingEdge");
  return StatusCode::SUCCESS;
}

bool FEB_v1::clockFallingEdge( int fe , int ch ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(4+ch)>>8)&1;
  info("clock Falling Edge FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(val),"FEB_v1::clockFallingEdge");
  return (bool)(val);
}
//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setClock80MHzFallingEdge(bool value){
  m_seqPga->setSpiAdd(m_seqAddress);
  unsigned int data=m_seqPga->spiRead(1);
  data &= 0xFFEF;
  data |= (value<<4) & 0x10;
  if (m_seqPga->spiWrite(1,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Clock 80MHz Falling Edge : "+itos(value),"FEB_v1::setClock80MzFallingEdge");
  return StatusCode::SUCCESS;
}

bool FEB_v1::clock80MHzFallingEdge(){
  m_seqPga->setSpiAdd(m_seqAddress);
  int val = (m_seqPga->spiRead(1)>>4)&1;
  info("clock 80MHz Falling Edge : "+itos(val),"FEB_v1::clock80MHzFallingEdge");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setCalibCte( int fe, int ch, int value ){
  if (ch>3){
    warning("try to configure a channel that does not exist.","FEB_v1::setClockFallingEdge");
    return StatusCode::FAILURE;
  }
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=m_seqPga->spiRead(4+ch);
  data = data & (0xFF00);
  data += value;
  if (m_seqPga->spiWrite(4+ch,data).isFailure()){
    return StatusCode::FAILURE;
  }
  info("set Calibration constant "+itos(fe)+" - Ch "+itos(fe)+" : "+itos(value),"FEB_v1::setCalibCte");
  return StatusCode::SUCCESS;
}

int FEB_v1::calibCte( int fe , int ch ){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  int val = (m_seqPga->spiRead(4+ch))&0xFF;
  info("Calib Constante FE "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(val),"FEB_v1::calibCte");
  return (bool)(val);
}

//=============================================================================
//
//=============================================================================

void FEB_v1::latencyLLT(){
  m_seqPga->setSpiAdd(m_seqAddress);
  int latency = m_seqPga->spiRead(3);
  m_latency0=(latency>>12)&0xF;
  m_latency1=(latency>>8)&0xF;
  m_latency2=(latency>>4)&0xF;
  m_latency3=latency&0xF;
  info("LLT Channel latency : "+itos(m_latency0));
  info("LLT Up nb   latency : "+itos(m_latency1));
  info("LLT Side nb latency : "+itos(m_latency2));
  info("LLT Corner  latency : "+itos(m_latency3));
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setLatencyLLT(int val){
  m_seqPga->setSpiAdd(m_seqAddress);
  int latency = m_seqPga->spiRead(3);
  latency &=0xFFF;
  latency |=((val&0xF)<<12);
   if (m_seqPga->spiWrite(3,latency).isFailure()){
    return StatusCode::FAILURE;
  }
   m_latency0=val;
  return StatusCode::SUCCESS;   
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setLatencyLLTUpNb(int val){
  m_seqPga->setSpiAdd(m_seqAddress);
  int latency = m_seqPga->spiRead(3);
  latency &=0xF0FF;
  latency |=((val&0xF)<<8);
   if (m_seqPga->spiWrite(3,latency).isFailure()){
    return StatusCode::FAILURE;
  }
   m_latency1=val;
  return StatusCode::SUCCESS;   
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setLatencyLLTSideNb(int val){
  m_seqPga->setSpiAdd(m_seqAddress);
  int latency = m_seqPga->spiRead(3);
  latency &=0xFF0F;
  latency |=((val&0xF)<<4);
   if (m_seqPga->spiWrite(3,latency).isFailure()){
    return StatusCode::FAILURE;
  }
   m_latency2=val;
  return StatusCode::SUCCESS;   
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setLatencyLLTCorner(int val){
  m_seqPga->setSpiAdd(m_seqAddress);
  int latency = m_seqPga->spiRead(3);
  latency &=0xFFF0;
  latency |=val&0xF;
   if (m_seqPga->spiWrite(3,latency).isFailure()){
    return StatusCode::FAILURE;
  }
   m_latency3=val;
  return StatusCode::SUCCESS;   
}


//=============================================================================
//
//=============================================================================

void FEB_v1::maskLLT(){
  m_seqPga->setSpiAdd(m_seqAddress);
  m_mask0=m_seqPga->spiRead(4);
  m_mask1=m_seqPga->spiRead(5);
  m_mask2=m_seqPga->spiRead(6);
  for (int i = 0; i<16; ++i){
    info("Channel "+itos(i)+" masked status : "+itos((m_mask0>>i)&1));
  }
  for (int i = 0; i<16; ++i){
    info("Channel "+itos(i+16)+" masked status : "+itos((m_mask1>>i)&1));
  }  
  for (int i = 0; i<4; ++i){
    info("Up Neig "+itos(i)+" masked status : "+itos((m_mask2>>(i+12))&1));
  }
  for (int i = 0; i<8; ++i){
    info("Sd Neig "+itos(i)+" masked status : "+itos((m_mask2>>(i+4))&1));
  }
  info("Corner masked status : "+itos((m_mask2>>3)&1));
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setMaskLLT(int ch, bool val){
  m_seqPga->setSpiAdd(m_seqAddress);
  if (ch<16) {
    m_mask0=m_seqPga->spiRead(4);
    if (val)  m_mask0 |= 1 << ch  ;
    else      m_mask0 &= ~(1<<ch) ;
        if (m_seqPga->spiWrite(4,m_mask0).isFailure()){
      return StatusCode::FAILURE;
    }
    return StatusCode::SUCCESS;  
  }
  else if (ch<32) {
    m_mask1=m_seqPga->spiRead(5);
    if (val)  m_mask1 |= 1 << (ch-16)  ;
    else      m_mask1 &= ~(1<<(ch-16)) ;
    if (m_seqPga->spiWrite(5,m_mask1).isFailure()){
      return StatusCode::FAILURE;
    }
    return StatusCode::SUCCESS;  
  }
  return StatusCode::FAILURE;  
}

//=============================================================================
//
//=============================================================================
StatusCode FEB_v1::setMaskLLTCorner(bool val){
  m_seqPga->setSpiAdd(m_seqAddress);
  m_mask2=m_seqPga->spiRead(6);
  if (val)  m_mask2 |= (1 << 3)  ;
  else      m_mask2 &= ~(1<<3) ;
  if (m_seqPga->spiWrite(6,m_mask2).isFailure()){
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;  
}

//=============================================================================
//
//=============================================================================
StatusCode FEB_v1::setMaskLLTUpNb(int ch, bool val){
  m_seqPga->setSpiAdd(m_seqAddress);
  m_mask2=m_seqPga->spiRead(6);
  if (val)  m_mask2 |= (1 << (12+ch))  ;
  else      m_mask2 &= ~(1<< (12+ch)) ;
  if (m_seqPga->spiWrite(6,m_mask2).isFailure()){
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;  
}

//=============================================================================
//
//=============================================================================
StatusCode FEB_v1::setMaskLLTSideNb(int ch, bool val){
  m_seqPga->setSpiAdd(m_seqAddress);
  m_mask2=m_seqPga->spiRead(6);
  if (val)  m_mask2 |= (1 << (4+ch))  ;
  else      m_mask2 &= ~(1<< (4+ch)) ;
  if (m_seqPga->spiWrite(6,m_mask2).isFailure()){
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtMode(int gbt, int mode ){
  std::string modes[4] = {
    "Normal operating mode",
    "Fixed pattern mode",
    "30 bit counter",
    "7 bit shift register"
  };
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  if (m_seqPga->i2cWrite(28, mode).isFailure()){
    warning("Cannot set Tx mode of the GBT "+itos(gbt)+
     " to "+modes[mode]+" ["+itos(mode)+"]");
    return StatusCode::FAILURE;
  }
  info("Setting Tx mode of the GBT "+itos(gbt)+
       " to "+modes[mode]+" ["+itos(mode)+"]");
  return StatusCode::SUCCESS;  
}

int FEB_v1::gbtMode( int gbt ){
  std::string modes[4] = {
    "Normal operating mode",
    "Fixed pattern mode",
    "30 bit counter",
    "7 bit shift register"
  };
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int mode = m_seqPga->i2cRead(28);
  info("Tx mode of the GBT "+itos(gbt)+
       " is : "+modes[mode]+" ["+itos(mode)+"]");
  return mode; 
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtDataPath(int gbt, int tx0, int tx1, int tx2){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = (tx2<<4)+(tx1<<2)+tx0; 
  if (m_seqPga->i2cWrite(29, wd).isFailure()){
    warning("Cannot set data path (A) of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(30, wd).isFailure()){
    warning("Cannot set data path (B) of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(31, wd).isFailure()){
    warning("Cannot set data path (C) of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  info("Setting data path of the GBT "+itos(gbt)+" to "+itos(wd));
  return StatusCode::SUCCESS;
}

int FEB_v1::gbtDataPath( int gbt ){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int mode = m_seqPga->i2cRead(29);
  info("Data Path (A) of the GBT "+itos(gbt)+" is "+itos(mode));
  info("Data Path (B) of the GBT "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(30)));
  info("Data Path (C) of the GBT "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(31)));
  return mode; 
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtTrackMode(int gbt, int mode){
  std::string str_mode[3]={
    "Static phase selection",
    "Training mode",
    "Automatic phase tracking"
  };
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = (mode<<4)+(mode<<2)+mode;
  if (m_seqPga->i2cWrite(62, wd).isFailure()){
    warning("Cannot set GBT track mode of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  info("Setting track mode of the GBT "+itos(gbt)+" to "+itos(wd)+" -> "+str_mode[mode&0b11]);
  return StatusCode::SUCCESS;
}

int FEB_v1::gbtTrackMode( int gbt ){
  std::string str_mode[3]={
    "Static phase selection",
    "Training mode",
    "Automatic phase tracking"
  };
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int mode = m_seqPga->i2cRead(62);
  info("Track mode of the GBT "+itos(gbt)+" is : "+itos(mode)+" -> "+str_mode[mode&0b11]); 
  return mode; 
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtTermEport(int gbt, bool term){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = 0xff;
  if (!term){
    wd = 0;
  }
  if (m_seqPga->i2cWrite(320, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(321, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(322, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(323, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(324, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(325, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(326, wd).isFailure()){
    warning("Cannot set GBT Term Eport 320 of the GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  info("Setting Eport Termination of the GBT "+itos(gbt)+" to "+itos(wd&1));
  return StatusCode::SUCCESS;
}

bool FEB_v1::gbtTermEport( int gbt ){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  info("Eport termination of the GBT (320) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(320)&1));
  info("Eport termination of the GBT (321) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(321)&1));
  info("Eport termination of the GBT (322) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(322)&1));
  info("Eport termination of the GBT (323) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(323)&1));
  info("Eport termination of the GBT (324) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(324)&1));
  info("Eport termination of the GBT (325) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(325)&1));
  info("Eport termination of the GBT (326) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(326)&1));
  return m_seqPga->i2cRead(320)&1;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbt80MHzClkEport(int gbt){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = (1<<4)+(1<<2)+1;
  if (m_seqPga->i2cWrite(63, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(87, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(111, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(135, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(159, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(183, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(207, wd).isFailure()){
    warning("Cannot set GBT Eport clock at 80MHz for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  info("Setting Eport clock at 80MHz for the GBT "+itos(gbt));
  return StatusCode::SUCCESS;
}

bool FEB_v1::gbt80MHzClkEport( int gbt ){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int mode = m_seqPga->i2cRead(63);
  info("Eport clock for the GBT (63)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(63)));
  info("Eport clock for the GBT (87)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(87)));
  info("Eport clock for the GBT (111) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(111)));
  info("Eport clock for the GBT (135) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(135)));
  info("Eport clock for the GBT (159) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(159)));
  info("Eport clock for the GBT (183) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(183)));
  info("Eport clock for the GBT (207) "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(207)));
  return mode; 
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtDLLEport(int gbt){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd1 = 0b1011;
  int wd0 = (wd1<<4)+wd1;
  if (m_seqPga->i2cWrite(64, wd0).isFailure()){
    warning("Cannot set DLL charge pump (64) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(65, wd1).isFailure()){
    warning("Cannot set DLL charge pump (65) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(88, wd0).isFailure()){
    warning("Cannot set DLL charge pump (88) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(89, wd1).isFailure()){
    warning("Cannot set DLL charge pump (89) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(112, wd0).isFailure()){
    warning("Cannot set DLL charge pump (112) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(113, wd1).isFailure()){
    warning("Cannot set DLL charge pump (113) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(136, wd0).isFailure()){
    warning("Cannot set DLL charge pump (136) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(137, wd1).isFailure()){
    warning("Cannot set DLL charge pump (137) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(160, wd0).isFailure()){
    warning("Cannot set DLL charge pump (160) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(161, wd1).isFailure()){
    warning("Cannot set DLL charge pump (161) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(184, wd0).isFailure()){
    warning("Cannot set DLL charge pump (184) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(185, wd1).isFailure()){
    warning("Cannot set DLL charge pump (185) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(208, wd0).isFailure()){
    warning("Cannot set DLL charge pump (208) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(209, wd1).isFailure()){
    warning("Cannot set DLL charge pump (209) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(231, wd0).isFailure()){
    warning("Cannot set DLL charge pump (231) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(232, wd1).isFailure()){
    warning("Cannot set DLL charge pump (232) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  if (m_seqPga->i2cWrite(233, 7).isFailure()){
    warning("Cannot set DLL charge pump (232) for GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  info("Setting DLL Eport for the GBT "+itos(gbt));
  info("Setting Phase aligner lock detection mode for GBT "+itos(gbt));
  return StatusCode::SUCCESS;
}

void FEB_v1::gbtDLLEport( int gbt ){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  info("Eport DLL Charge pump for the GBT (64)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(64)));
  info("Eport DLL Charge pump for the GBT (65)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(65)));
  info("Eport DLL Charge pump for the GBT (88)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(88)));
  info("Eport DLL Charge pump for the GBT (89)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(89)));
  info("Eport DLL Charge pump for the GBT (112)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(112)));
  info("Eport DLL Charge pump for the GBT (113)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(113)));
  info("Eport DLL Charge pump for the GBT (136)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(136)));
  info("Eport DLL Charge pump for the GBT (137)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(137)));
  info("Eport DLL Charge pump for the GBT (160)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(160)));
  info("Eport DLL Charge pump for the GBT (161)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(161)));
  info("Eport DLL Charge pump for the GBT (184)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(184)));
  info("Eport DLL Charge pump for the GBT (185)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(185)));
  info("Eport DLL Charge pump for the GBT (208)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(208)));
  info("Eport DLL Charge pump for the GBT (209)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(209)));
  info("Eport DLL Charge pump for the GBT (231)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(231)));
  info("Eport DLL Charge pump for the GBT (232)  "+itos(gbt)+" is "+itos(m_seqPga->i2cRead(232)));  
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtEnableEport(int gbt, bool enable){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = 0xff;
  if (!enable){
    wd = 0;
  }
  int ports[21]={81, 82, 83, 105, 106, 107, 129, 130, 131, 153, 154,
         155, 177, 178, 179, 201, 202, 203, 225, 226, 227};
  for (int i=0; i<21; ++i){
    if (m_seqPga->i2cWrite(ports[i], wd).isFailure()){
      warning("Cannot set (en)able eport ("+itos(ports[i])+") of GBT "+itos(gbt));
      return StatusCode::FAILURE;
    }
  };
  if (enable){
    info("Enabling Eports for the GBT "+itos(gbt));
  }
  else
  {
    info("Disabling Eports for the GBT "+itos(gbt));
  }
  return StatusCode::SUCCESS;
}

bool FEB_v1::gbtEnableEport( int gbt ){
  int ports[21]={81, 82, 83, 105, 106, 107, 129, 130, 131, 153, 154,
         155, 177, 178, 179, 201, 202, 203, 225, 226, 227};
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  for (int i = 0; i<21; ++i){
    info("Eport enable ("+itos(ports[i])+") for the GBT "+itos(gbt)+" : "+itos(m_seqPga->i2cRead(ports[i])));
  }
  return m_seqPga->i2cRead(ports[0])&1;
}
//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setGbtClockStrength(int gbt, int strength){
  info("Setting the gbt "+itos(gbt)+" output clock strength to "+itos(strength));
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int wd = ((strength&0xF)<<4)+(strength&0xF);
  int ports[4]={ 269, 270, 271, 272 };
  for (int i=0; i<4; ++i){
    if (m_seqPga->i2cWrite(ports[i], wd).isFailure()){
      warning("Cannot set gbt output clock strength ("+itos(ports[i])+") of GBT "+itos(gbt));
      return StatusCode::FAILURE;
    }
  };
  return StatusCode::SUCCESS;
}

int FEB_v1::gbtClockStrength(int gbt){
  int ports[4]={ 269, 270, 271, 272 };
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int val0 = m_seqPga->i2cRead(ports[0])&0xF; 
  int val1 = m_seqPga->i2cRead(ports[1])&0xF; 
  int val2 = m_seqPga->i2cRead(ports[2])&0xF; 
  int val3 = m_seqPga->i2cRead(ports[3])&0xF; 
  if ( val1 != val0 || val2 != val0 || val3 != val0 ){
      warning("Output clock strength registers are not identical");
      return -1;
  }
  if ( (val0&0xF) != ((val0&0xF0)>>4)){
      warning("Output clock strength registers are not identical");
      return -1;
    }
  return val0&0xF;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setOutputEport(int gbt, int latency, int clock){
  m_seqPga->setSpiAdd(m_seqAddress);
  unsigned int data=(clock&0xFF)+((latency&0xFF)<<8);
  if (m_seqPga->spiWrite(20+gbt,data).isFailure()){
    warning("Cannot set Output EPort phase FPGA Seq - GBT "+itos(gbt)+" : "+itos(data),"FEB_v1::setOutputEPort");
    return StatusCode::FAILURE;
  }
  info("set Output EPort phase FPGA Seq - GBT "+itos(gbt)+" : "+itos(data),"FEB_v1::setOutputEPort");
  return StatusCode::SUCCESS;
}

int FEB_v1::clockPhaseEport (int gbt){
  m_seqPga->setSpiAdd(m_seqAddress);
  return ((m_seqPga->spiRead(20+gbt)>>8)&0xFF);
}

int FEB_v1::latencyEport (int gbt){
  m_seqPga->setSpiAdd(m_seqAddress);
  return (m_seqPga->spiRead(20+gbt)&0xFF);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::setOutputEport(int fe, int ch, int latency, int clock){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  unsigned int data=(clock&0x3F)+((latency&0x3F)<<6);
  if (m_seqPga->spiWrite(14+ch,data).isFailure()){
    warning("Cannot set Output EPort phase FPGA"+itos(fe)+" - Ch "+itos(ch)+" : "+itos(data),"FEB_v1::setOutputEPort");
    return StatusCode::FAILURE;
  }
  info("set Output EPort phase FPGA "+itos(fe)+" - Ch "+itos(ch)+" : "+itos(data),"FEB_v1::setOutputEPort");
  return StatusCode::SUCCESS;
}

int FEB_v1::clockPhaseEport (int fe, int ch){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  return ((m_seqPga->spiRead(14+ch)>>6)&0x3F);
}

int FEB_v1::latencyEport (int fe, int ch){
  m_seqPga->setSpiAdd(m_feAddress[fe]);
  return (m_seqPga->spiRead(14+ch)&0x3F);
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::gbtDLLReset(int gbt){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int registers[8]={
    65, 89, 113, 137, 161, 185, 209, 232
  };
  int zero = 0;
  int one  = 7;
  for ( int i =0; i<8; ++i){
    int val  = m_seqPga->i2cRead(registers[i]);
    int val0 = val & (0b10001111);
    int val1 = val | (0b1110000);
    StatusCode stat1 = m_seqPga->i2cWrite(registers[i], val1);
    StatusCode stat0 = m_seqPga->i2cWrite(registers[i], val0);
    if (stat0.isFailure() || stat1.isFailure()){
      warning("Could not reset DLL register "+itos(registers[i])+" of GBT "+itos(gbt));
      return StatusCode::FAILURE;
    }
  }
  info("Reset of the DLL of GBT "+itos(gbt));
  return StatusCode::SUCCESS;
}

//=============================================================================
//
//=============================================================================

int FEB_v1::gbtStatus(int gbt){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  int status_gbt = (m_seqPga->i2cRead(431) >> 2);
  if (status_gbt==24){
    info("GBT status is 0d"+ itos(status_gbt),"GBT Config");
  }
  else {
    error("GBT status is 0d"+ itos(status_gbt),"GBT Config");
  }
  return status_gbt;
}

//=============================================================================
//
//=============================================================================

StatusCode FEB_v1::gbtAcknowledgeConfig(int gbt){
  m_seqPga->setI2cAdd(m_gbtAddress[gbt]);
  if (m_seqPga->i2cWrite(365, 170).isFailure()){
    warning("Cannot acknowledge configuration of GBT "+itos(gbt));
    return StatusCode::FAILURE;
  }
  return StatusCode::SUCCESS;
}

//=============================================================================