FEB_v1.h

Go to the documentation of this file.

// $Id: $
#ifndef INC_FEB_V1_H
#define INC_FEB_V1_H 1

// Include files
#include "Element.h"
#include "Data.h"
#include "RAM.h"
#include "UsbFTMLInterface.h"
#include "SeqPGA.h"
//#include "UsbI2cBus.h"
//#include "UsbSpiBus.h"

class FEB_v1 : public Element {
public:
  FEB_v1( );

  virtual ~FEB_v1( ); 

  void help() { info("FEB_v1 "+name()+". No help.","FEB_v1::help"); };

  StatusCode init() {
    return StatusCode::SUCCESS;
  };

  void reset() {
    m_seqPga->reset();
    debug("FEB_v1 "+name()+" reset.","FEB_v1::reset");
  };

  void resetSpi() {
    m_seqPga->resetSpi();
    debug("FEB_v1 "+name()+" reset Spi.","FEB_v1::resetSpi");
  };

  void update () {info("FEB_v1 "+name()+". Nothing to do.","FEB_v1::update");};

  SeqPGA* seqPga(){
    return m_seqPga;
  }

  StatusCode setSpyModeSeq(bool);
  bool       spyModeSeq();
  StatusCode setSpyModeFE(int, bool);
  bool       spyModeFE(int);
  StatusCode setDisableSubtract(int, bool);
  bool       disableSubtract(int);
  StatusCode setOldSubtract(int, bool);
  bool       oldSubtract(int);
  StatusCode setThreshold(int, int);
  int        threshold(int);
  StatusCode setLatency(int, int);
  int        latency(int);
  StatusCode setInjectModeFE(int, bool);
  bool       injectModeFE(int);
  StatusCode setProbeEnable(int, bool);
  void       probeEnable();
  StatusCode setSpareForTrigEnable(int, int);
  int        spareForTrigEnable(int);
  StatusCode setTestDuration(int);
  int        testDuration(int fpga);
  StatusCode setStopInjLoop(bool);
  bool       stopInjLoop(int);
  StatusCode setEnableBXIDReset( bool );
  bool       enableBXIDReset();  
  
  StatusCode setGain4( int, int, bool );
  StatusCode setPseudoADCEnable( int, int , bool);
  StatusCode setPseudoPMEnable( int, int, bool);
  StatusCode setGlobalPseudoPMEnable( int, bool);
  StatusCode setClockFallingEdge( int, int , bool);
  StatusCode setClock80MHzFallingEdge(bool);
  StatusCode setCalibCte( int, int , int);
  
  bool gain4( int, int );
  bool pseudoADCEnable( int, int );
  bool pseudoPMEnable( int, int );
  bool globalPseudoPMEnable( int );
  bool clockFallingEdge( int, int );
  bool clock80MHzFallingEdge( );
  int  calibCte( int, int );
  
  StatusCode testSequence() { return m_seqPga->testSequence(); }
  
  StatusCode setExtTrig( bool trig ) { return m_seqPga->setExtTrig( trig ); }
  bool extTrig( ) { return m_seqPga->extTrig( ); }

  void readFifo( int, int , unsigned int*);
  void readFifoSpyFE( int fe, int dump);
  void readFifoLLTFE( int fe, int dump);
  void readFifoInjectFE( int fe, int dump);
  void readFifoLLT(int dump);
  void maskLLT();
  void latencyLLT();
  StatusCode setMaskLLT(int, bool);
  StatusCode setMaskLLTCorner(bool);
  StatusCode setMaskLLTUpNb(int, bool);
  StatusCode setMaskLLTSideNb(int, bool);
  StatusCode setLatencyLLT(int);
  StatusCode setLatencyLLTCorner(int);
  StatusCode setLatencyLLTUpNb(int);
  StatusCode setLatencyLLTSideNb(int);

  StatusCode setOutputEport(int, int, int);
  int        latencyEport(int);
  int        clockPhaseEport(int);

  StatusCode setOutputEport(int, int, int, int);
  int        latencyEport(int, int);
  int        clockPhaseEport(int, int);
  
  void writeFifoSpyFE( int fe );
  void writeFifoLLTFE( int fe );
  void writeFifoInjectFE( int fe , int pattern);
  void writeDataFifoInjectFE( int , int *, int*, int*, int*);
  void writeFifoLLT();
  StatusCode resetFifoSpyFE( int  );
  StatusCode resetFifoInjectFE( int  );
  StatusCode resetFE( int  );
  int statusRegister( int  );

  Data* data(){ return m_data; }
  RAM*  ramInj(int i){
    return m_ramInj[i];
  }
  RAM*  ramSpy(int i){
    return m_ramSpy[i];
  }
  

  StatusCode setGbtMode(int, int);
  int        gbtMode(int);
  StatusCode setGbtDataPath(int, int, int, int);
  int        gbtDataPath(int);
  StatusCode setGbtTrackMode(int, int);
  int        gbtTrackMode(int);
  StatusCode setGbtTermEport(int,bool);
  bool       gbtTermEport(int);
  StatusCode setGbt80MHzClkEport(int);
  bool       gbt80MHzClkEport(int);
  StatusCode setGbtDLLEport(int);
  void       gbtDLLEport(int);
  StatusCode setGbtEnableEport(int, bool);
  bool       gbtEnableEport(int);
  int        gbtStatus(int);
  StatusCode setGbtClockStrength(int, int);
  int        gbtClockStrength(int);
  StatusCode gbtDLLReset(int);
  StatusCode gbtAcknowledgeConfig(int);

 protected:

private:
  int               m_fifoDepth;
  int               m_seqAddress;
  int               m_feAddress[8];
  int               m_gbtAddress[4];
  int               m_icecalAddress[8];
  int               m_fifoSpyAddress[3];
  int               m_fifoLLTAddress[3];
  int               m_fifoInjectAddress[3];
  int               m_fifoTrigAddress[3];
  SeqPGA           *m_seqPga;
  unsigned int     *m_fifo[3];
  int              *m_ch[4];
  Data             *m_data;
  int               m_mask0;
  int               m_mask1;
  int               m_mask2;
  int               m_latency0;
  int               m_latency1;
  int               m_latency2;
  int               m_latency3;
  RAM              *m_ramInj[3];
  RAM              *m_ramSpy[3];
  RAM              *m_fifoUsbTest;
};

#endif // INC_FEB_V1_H